Freescale Semiconductor MPC8260 - Manual (Page 1332)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-4 Freescale Semiconductor
C–C Index
BISYNC mode, 23-12
definition, 31-22
fast communications controllers (FCCs)
Fast Ethernet mode
receive, 35-22
transmit, 35-25
HDLC mode
receive, 36-9
transmit, 36-12
overview
receive, 29-10
transmit, 29-10
GCI mode
monitor channel, 27-32
HDLC mode, 22-8
I
2
C controller
receive, 39-12
transmit, 39-13
IDMA emulation
auto buffer, 19-16
IDMA buffers, 19-24
multi-channel controllers (MCCs)
receive, 28-43
transmit, 28-45
overview, 20-10, 31-36
serial management controllers (SMCs), 27-4
serial peripheral interface (SPI)
receive, 38-14
transmit, 38-15
transparent mode
serial communications controllers (SCCs), 24-8
serial management controllers (SMCs), 27-26
UART mode
serial communications controllers (SCCs), 21-14
serial management controllers (SMCs), 27-13
Buffers
BUFCMD, 11-42
Bus interface
hierarchical bus interface example, 11-101
BxTx (byte-select signals), 11-75
Byte stuffing, 23-1
Byte-select signals, 11-75
C
Cascaded mode, 18-3
CHAMR (channel mode register), 28-8
CHAMR (channel mode register, transparent mode), 28-13,
28-15
Chip-select
assertion timing, 11-53
chip-select machine, 11-51
signals, 11-74
write enable deassertion timing, 11-54
Clocks
basic power structure, 10-11
clock divider, 10-5
clock unit, 10-1
external clock inputs, 10-1
general system clocks, 10-5
input clock interface, 10-1
internal clock signals, 10-5
main PLL, 10-2
memory map, 3-7
OSCM, 10-1
overview, 10-1
PLL block diagram, 10-2
PLL pins, 10-6
SCCR, 10-8
SCMR, 10-9
skew elimination, 10-3
clocks and reset keys memory map,, 3-4
CMXFCR (CMX FCC clock route register), 16-13
CMXSCR (CMX SCC clock route register), 16-16
CMXSI1CR (CMX SI1 clock route register), 16-12
CMXSI2CR (CMX SI2 clock route register), 16-12
CMXSMR (CMX SMC clock route register), 16-19
CMXUAR (CMX UTOPIA address register), 16-7
Commands
ATM TRANSMIT command, 30-93
fast communications controllers (FCCs)
Ethernet mode
receive commands, 35-12
transmit commands, 35-12
HDLC mode
receive commands, 36-6
transmit commands, 36-5
I
2
C controller, 39-11
IDMA emulation, 19-27
serial peripheral interface (SPI), 38-12
communication processor module
features, 34-7
Communications processor (CP)
block diagram, 14-6
execution from RAM, 14-8
features list, 14-4
memory map, 3-16
microcode execution from RAM, 14-8
microcode revision number, 14-12
peripheral interface, 14-7
RCCR, 14-8
REV_NUM, 14-12
RTSCR, 14-11
RTSR, 14-11
Communications processor module (CPM)