Freescale Semiconductor MPC8260 - Manual (Page 885)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 28-37
desired interrupt handler latency or other factors. It is up to the user to determine an interrupt handling
scheme that provides desired performance and functionality.
28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)
The MCC event register (MCCE) is used to report events and generate interrupt requests. For each of its
flags, a programmable mask/enable bit in MCCM determines whether an interrupt request is generated.
The MCC mask register (MCCM) is used to enable/disable interrupt requests. For each flag in the MCCE
there is a programmable mask/enable bit in MCCM which determines whether an interrupt request is
generated. Setting an MCCM bit enables and clearing an MCCM bit disables the corresponding interrupt.
MCCE bits are cleared by writing ones to them; writing zeros has no effect.
Figure 28-19 shows MCCE and MCCM bits.
Table 28-18 describes MCCE fields.
0 1 2 3 4 5 6 7 8 11 12 13 14 15
Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3 — TQOV TINT GUN GOV
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x11B30 (MCCE1), 0x0x11B50 (MCCE2)/0x0x11B34 (MCCM1), 0x0x11B54 (MCCM2)
Figure 28-19. MCC Event Register (MCCE)/Mask Register (MCCM)
Table 28-18. MCCE/MCCM Register Field Descriptions
Bits Name Description
0 QOV0 QOVx—Receive interrupt queue overflow. IQOV is set (and an interrupt request generated) by the CP
whenever an overflow occurs in the transmit circular interrupt table. This occurs if the CP tries to
update an interrupt entry that was not handled by the user (such an entry is identified by V = 1).
RINTx—Receive interrupt. When RINT = 1, the MCC generated at least one new entry in the receive
interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt circular
table and starts processing a specific channel’s exception. The user returns from the interrupt handler
when it reaches a table entry with V = 0.
1 RINT0
2 QOV1
3 RINT1
4 QOV2
5 RINT2
6 QOV3
7 RINT3
8–11 — Reserved, should be cleared.
12 TQOV Transmit interrupt queue overflow. TQOV is set (and interrupt request generated) by the CP whenever
an overflow occurs in the transmit circular interrupt table. This condition occurs if the CP attempts to
write a new interrupt entry into an entry that was not handled by the user. Such an entry is identified
by V = 1.