Freescale Semiconductor MPC8260 - Manual (Page 935)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-15
30.4.2 Address Compression
The address compression mechanism uses two levels of address translation to help minimize the memory
space needed to cover the available address range. The first level of translation (VP-level) uses a look-up
table based on the 4-bit PHY address and the 12-bit virtual path identifier; the second level (VC-level) uses
the 16-bit virtual channel identifier. If there is no match during address compression, the cell is considered
a misinserted cell.
During the VP-level translation, VP_MASK in the ATM parameter RAM compresses an incoming cell’s
PHY address and VPI to create an index into the VP-level table. The VP-level table entry consists of
another mask (VC_MASK) and a pointer to one of the VC-level tables (VCOFFSET). Note that the VP
table should reside in the dual-port RAM.
In the VC-level translation, the VCI is compressed with the VC_MASK to generate a pointer to the
VC-level table entry containing the received cell’s channel code. The VC table should reside in external
memory.
Figure 30-5 shows an example of address compression.
Figure 30-5. Address Compression Mechanism
Figure 30-5 shows VP_MASK selecting five VPI bits to index the VP-level table. The VP-level table entry
contains the 16-bit mask (VC_MASK) and the VC-level table offset (VCOFFSET) for the next level of
address mapping. The VC_MASK selects VCI bits 4–10, which is used with VCT_BASE and VCOFFSET
32-bit entries
VP-level addressing table
VPI
0000 00011111
VPpointer
VPT_BASE
VCOFFSET VC_MASK
VCI
00000111 11110000
VCpointer
32-bit entries
VC-level addressing tables
VCT_BASE
VP_MASK
16 bit 16 bit
PHY Addr
0000
16 bit
12 bit 4 bit
(in external memory)
(in dual-port RAM recommended)
Ch Code[15–0] —
16 bit 15 bit
MS
1 bit
31 0
31 0
0b00011