Document Outline

• MPC8260 PowerQUICC™ II Family Reference Manual
• About This Book
  • Reference Manual Revision History
  • Before Using this Manual-Important Note
  • Audience
  • Organization
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
  • PowerPC Architecture Terminology Conventions
• Part I Overview
  • Intended Audience
  • Contents
  • Conventions
  • Acronyms and Abbreviations
• Chapter 1 Overview
  • 1.1 Features
  • 1.2 Architecture Overview
    • Figure 1-1. PowerQUICC II Block Diagram
    • 1.2.1 G2 Core
    • 1.2.2 System Interface Unit (SIU)
    • 1.2.3 Communications Processor Module (CPM)
  • 1.3 Software Compatibility Issues
    • 1.3.1 Signals
      • Figure 1-2. PowerQUICC II External Signals
  • 1.4 Differences between MPC860 and PowerQUICC II
  • 1.5 Serial Protocol Table
    • Table 1-1. PowerQUICC II Serial Protocols
  • 1.6 PowerQUICC II Configurations
    • 1.6.1 Pin Configurations
    • 1.6.2 Serial Performance
      • Table 1-2. Serial Performance
      • Table 1-3. MPC8250 Serial Performance
  • 1.7 Application Examples
    • 1.7.1 Communication Systems
      • 1.7.1.1 Remote Access Server
        • Figure 1-3. Remote Access Server Configuration
      • 1.7.1.2 Regional Office Router
        • Figure 1-4. Regional Office Router Configuration
      • 1.7.1.3 LAN-to-WAN Bridge Router
        • Figure 1-5. LAN-to-WAN Bridge Router Configuration
      • 1.7.1.4 Cellular Base Station
        • Figure 1-6. Cellular Base Station Configuration
      • 1.7.1.5 Telecommunications Switch Controller
        • Figure 1-7. Telecommunications Switch Controller Configuration
      • 1.7.1.6 SONET Transmission Controller
        • Figure 1-8. SONET Transmission Controller Configuration
    • 1.7.2 Bus Configurations
      • 1.7.2.1 Basic System
        • Figure 1-9. Basic System Configuration
      • 1.7.2.2 High-Performance Communication
        • Figure 1-10. High-Performance Communication
      • 1.7.2.3 High-Performance System Microprocessor
        • Figure 1-11. High-Performance System Microprocessor Configuration
      • 1.7.2.4 PCI
        • Figure 1-12. PCI Configuration
      • 1.7.2.5 PCI with 155-Mbps ATM
        • Figure 1-13. PCI with 155-Mbps ATM Configuration
      • 1.7.2.6 PowerQUICC II as PCI Agent
        • Figure 1-14. PowerQUICC II as PCI Agent
• Chapter 2 G2 Core
  • 2.1 Overview
    • Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram
  • 2.2 G2 Processor Core Features
    • 2.2.1 Instruction Unit
    • 2.2.2 Instruction Queue and Dispatch Unit
    • 2.2.3 Branch Processing Unit (BPU)
    • 2.2.4 Independent Execution Units
      • 2.2.4.1 Integer Unit (IU)
      • 2.2.4.2 Floating-Point Unit (FPU)
      • 2.2.4.3 Load/Store Unit (LSU)
      • 2.2.4.4 System Register Unit (SRU)
    • 2.2.5 Completion Unit
    • 2.2.6 Memory Subsystem Support
      • 2.2.6.1 Memory Management Units (MMUs)
      • 2.2.6.2 Cache Units
  • 2.3 Programming Model
    • 2.3.1 Register Set
      • 2.3.1.1 PowerPC Register Set
        • Figure 2-2. PowerQUICC II Programming Model-Registers
      • 2.3.1.2 PowerQUICC II-Specific Registers
        • 2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)
          • Figure 2-3. Hardware Implementation Register 0 (HID0)
          • Table 2-1. HID0 Field Descriptions (continued)
        • 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)
          • Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)
          • Table 2-2. HID1 Field Descriptions
        • 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)
          • Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)
          • Table 2-3. HID2 Field Descriptions (continued)
        • 2.3.1.2.4 Processor Version Register (PVR)
    • 2.3.2 PowerPC Instruction Set and Addressing Modes
      • 2.3.2.1 Calculating Effective Addresses
      • 2.3.2.2 PowerPC Instruction Set
      • 2.3.2.3 PowerQUICC II Implementation-Specific Instruction Set
  • 2.4 Cache Implementation
    • 2.4.1 PowerPC Cache Model
    • 2.4.2 PowerQUICC II Implementation-Specific Cache Implementation
      • 2.4.2.1 Data Cache
        • Figure 2-6. Data Cache Organization
      • 2.4.2.2 Instruction Cache
      • 2.4.2.3 Cache Locking
        • 2.4.2.3.1 Entire Cache Locking
        • 2.4.2.3.2 Way Locking
  • 2.5 Exception Model
    • 2.5.1 PowerPC Exception Model
    • 2.5.2 PowerQUICC II Implementation-Specific Exception Model
      • Table 2-4. Exception Classifications for the Processor Core
      • Table 2-5. Exceptions and Conditions (continued)
    • 2.5.3 Exception Priorities
  • 2.6 Memory Management
    • 2.6.1 PowerPC MMU Model
    • 2.6.2 PowerQUICC II Implementation-Specific MMU Features
  • 2.7 Instruction Timing
    • Table 2-6. Integer Divide Latency
  • 2.8 Differences between the PowerQUICC II’s G2 Core and the MPC603e Microprocessor
    • Table 2-7. Major Differences between PowerQUICC II’s G2 Core and the MPC603e User’s Manual
• Chapter 3 Memory Map
  • Table 3-1. Internal Memory Map
• Part II Configuration and Reset
  • Intended Audience
  • Contents
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
• Chapter 4 System Interface Unit (SIU)
  • Figure 4-1. SIU Block Diagram
  • 4.1 System Configuration and Protection
    • Table 4-1. System Configuration and Protection Functions
    • Figure 4-2. System Configuration and Protection Logic
    • 4.1.1 Bus Monitor
    • 4.1.2 Timers Clock
      • Figure 4-3. Timers Clock Generation
    • 4.1.3 Time Counter (TMCNT)
      • Figure 4-4. TMCNT Block Diagram
    • 4.1.4 Periodic Interrupt Timer (PIT)
      • Figure 4-5. PIT Block Diagram
    • 4.1.5 Software Watchdog Timer
      • Figure 4-6. Software Watchdog Timer Service State Diagram
      • Figure 4-7. Software Watchdog Timer Block Diagram
  • 4.2 Interrupt Controller
    • 4.2.1 Interrupt Configuration
      • Figure 4-8. PowerQUICC II Interrupt Structure
      • 4.2.1.1 Machine Check Interrupt
      • 4.2.1.2 INT Interrupt
    • 4.2.2 Interrupt Source Priorities
      • Table 4-2. Interrupt Source Priority Levels (continued)
      • 4.2.2.1 SCC, FCC, and MCC Relative Priority
      • 4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority
      • 4.2.2.3 Highest Priority Interrupt
    • 4.2.3 Masking Interrupt Sources
      • Figure 4-9. Interrupt Request Masking
    • 4.2.4 Interrupt Vector Generation and Calculation
      • Table 4-3. Encoding the Interrupt Vector (continued)
      • 4.2.4.1 Port C External Interrupts
  • 4.3 Programming Model
    • 4.3.1 Interrupt Controller Registers
      • 4.3.1.1 SIU Interrupt Configuration Register (SICR)
        • Figure 4-10. SIU Interrupt Configuration Register (SICR)
        • Table 4-4. SICR Field Descriptions
      • 4.3.1.2 SIU Interrupt Priority Register (SIPRR)
        • Figure 4-11. SIU Interrupt Priority Register (SIPRR)
        • Table 4-5. SIPRR Field Descriptions
      • 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
        • Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)
        • Table 4-6. SCPRR_H Field Descriptions
        • Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)
        • Table 4-7. SCPRR_L Field Descriptions
      • 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
        • Figure 4-14. SIPNR_H
        • Figure 4-15. SIPNR_L
      • 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
        • Figure 4-16. SIMR_H
        • Figure 4-17. SIMR_L
      • 4.3.1.6 SIU Interrupt Vector Register (SIVEC)
        • Figure 4-18. SIU Interrupt Vector Register (SIVEC)
        • Figure 4-19. Interrupt Table Handling Example
      • 4.3.1.7 SIU External Interrupt Control Register (SIEXR)
        • Figure 4-20. SIU External Interrupt Control Register (SIEXR)
        • Table 4-8. SIEXR Field Descriptions
    • 4.3.2 System Configuration and Protection Registers
      • 4.3.2.1 Bus Configuration Register (BCR)
        • Figure 4-21. Bus Configuration Register (BCR)
        • Table 4-9. BCR Field Descriptions (continued)
      • 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)
        • Figure 4-22. PPC_ACR
        • Table 4-10. PPC_ACR Field Descriptions
      • 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
        • Figure 4-23. PPC_ALRH
        • Figure 4-24. PPC_ALRL
      • 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)
        • Figure 4-25. LCL_ACR
        • Table 4-11. LCL_ACR Field Descriptions (continued)
      • 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
        • Figure 4-26. LCL_ALRH
        • Figure 4-27. LCL_ALRL
      • 4.3.2.6 SIU Module Configuration Register (SIUMCR)
        • Figure 4-28. SIU Model Configuration Register (SIUMCR)
        • Table 4-12. SIUMCR Register Field Descriptions (continued)
      • 4.3.2.7 Internal Memory Map Register (IMMR)
        • Figure 4-29. Internal Memory Map Register (IMMR)
        • Table 4-13. IMMR Field Descriptions
      • 4.3.2.8 System Protection Control Register (SYPCR)
        • Figure 4-30. System Protection Control Register (SYPCCR)
        • Table 4-14. SYPCR Field Descriptions
      • 4.3.2.9 Software Service Register (SWSR)
      • 4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
        • Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
        • Table 4-15. TESCR1 Field Descriptions (continued)
      • 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
        • Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
        • Table 4-16. TESCR2 Field Descriptions
      • 4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
        • Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
        • Table 4-17. L_TESCR1 Field Descriptions (continued)
      • 4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
        • Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
        • Table 4-18. L_TESCR2 Field Descriptions
      • 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
        • Figure 4-35. Time Counter Status and Control Register (TMCNTSC)
        • Table 4-19. TMCNTSC Field Descriptions
      • 4.3.2.15 Time Counter Register (TMCNT)
        • Figure 4-36. Time Counter Register (TCMCNT)
      • 4.3.2.16 Time Counter Alarm Register (TMCNTAL)
        • Figure 4-37. Time Counter Alarm Register (TMCNTAL)
        • Table 4-20. TMCNTAL Field Descriptions
    • 4.3.3 Periodic Interrupt Registers
      • 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)
        • Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)
        • Table 4-21. PISCR Field Descriptions
      • 4.3.3.2 Periodic Interrupt Timer Count Register (PITC)
        • Figure 4-39. Periodic interrupt Timer Count Register (PITC)
        • Table 4-22. PITC Field Descriptions
      • 4.3.3.3 Periodic Interrupt Timer Register (PITR)
        • Figure 4-40. Periodic Interrupt Timer Register (PITR)
        • Table 4-23. PITR Field Descriptions
    • 4.3.4 PCI Control Registers
      • 4.3.4.1 PCI Base Register (PCIBRx)
        • Figure 4-41. PCI Base Registers (PCIBRx)
        • Table 4-24. PCIBRx Field Descriptions
      • 4.3.4.2 PCI Mask Register (PCIMSKx)
        • Figure 4-42. PCI Mask Register (PCIMSKx)
        • Table 4-25. PCIMSKx Field Descriptions
  • 4.4 SIU Pin Multiplexing
    • Table 4-26. SIU Pins Multiplexing Control
• Chapter 5 Reset
  • 5.1 Reset Causes
    • Table 5-1. Reset Causes
    • 5.1.1 Reset Actions
      • Table 5-2. Reset Actions for Each Reset Source
    • 5.1.2 Power-On Reset Flow
      • Figure 5-1. Power-on Reset Flow
    • 5.1.3 HRESET Flow
    • 5.1.4 SRESET Flow
  • 5.2 Reset Status Register (RSR)
    • Figure 5-2. Reset Status Register (RSR)
    • Table 5-3. RSR Field Descriptions (continued)
  • 5.3 Reset Mode Register (RMR)
    • Figure 5-3. Reset Mode Register (RMR)
    • Table 5-4. RMR Field Descriptions
  • 5.4 Reset Configuration
    • Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued)
    • Table 5-6. Configuration EPROM Addresses
    • 5.4.1 Hard Reset Configuration Word
      • Figure 5-4. Hard Reset Configuration Word
      • Table 5-7. Hard Reset Configuration Word Field Descriptions (continued)
    • 5.4.2 Hard Reset Configuration Examples
      • 5.4.2.1 Single PowerQUICC II with Default Configuration
        • Figure 5-5. Single Chip with Default Configuration
      • 5.4.2.2 Single PowerQUICC II Configured from Boot EPROM
        • Figure 5-6. Configuring a Single Chip from EPROM
      • 5.4.2.3 Multiple PowerQUICC IIs Configured from Boot EPROM
        • Figure 5-7. Configuring Multiple Chips
      • 5.4.2.4 Multiple PowerQUICC IIs in a System with No EPROM
• Part III The Hardware Interface
  • Intended Audience
  • Contents
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
• Chapter 6 External Signals
  • 6.1 Functional Pinout
    • Figure 6-1. PowerQUICC II External Signals
  • 6.2 Signal Descriptions
    • Table 6-1. External Signals (continued)
• Chapter 7 60x Signals
  • 7.1 Signal Configuration
    • Figure 7-1. Signal Groupings
  • 7.2 Signal Descriptions
    • 7.2.1 Address Bus Arbitration Signals
      • 7.2.1.1 Bus Request (BR)-Output
        • 7.2.1.1.1 Address Bus Request (BR)-Output
        • 7.2.1.1.2 Address Bus Request (BR)-Input
      • 7.2.1.2 Bus Grant (BG)
        • 7.2.1.2.1 Bus Grant (BG)-Input
        • 7.2.1.2.2 Bus Grant (BG)-Output
      • 7.2.1.3 Address Bus Busy (ABB)
        • 7.2.1.3.1 Address Bus Busy (ABB)-Output
        • 7.2.1.3.2 Address Bus Busy (ABB)-Input
    • 7.2.2 Address Transfer Start Signal
      • 7.2.2.1 Transfer Start (TS)
        • 7.2.2.1.1 Transfer Start (TS)-Output
      • 7.2.2.2 Transfer Start (TS)-Input
    • 7.2.3 Address Transfer Signals
      • 7.2.3.1 Address Bus (A[0-31])
        • 7.2.3.1.1 Address Bus (A[0-31])-Output
        • 7.2.3.1.2 Address Bus (A[0-31])-Input
    • 7.2.4 Address Transfer Attribute Signals
      • 7.2.4.1 Transfer Type (TT[0-4])
        • 7.2.4.1.1 Transfer Type (TT[0-4])-Output
        • 7.2.4.1.2 Transfer Type (TT[0-4])-Input
      • 7.2.4.2 Transfer Size (TSIZ[0-3])
      • 7.2.4.3 Transfer Burst (TBST)
      • 7.2.4.4 Global (GBL)
        • 7.2.4.4.1 Global (GBL)-Output
        • 7.2.4.4.2 Global (GBL)-Input
      • 7.2.4.5 Caching-Inhibited (CI)-Output
      • 7.2.4.6 Write-Through (WT)-Output
    • 7.2.5 Address Transfer Termination Signals
      • 7.2.5.1 Address Acknowledge (AACK)
        • 7.2.5.1.1 Address Acknowledge (AACK)-Output
        • 7.2.5.1.2 Address Acknowledge (AACK)-Input
      • 7.2.5.2 Address Retry (ARTRY)
        • 7.2.5.2.1 Address Retry (ARTRY)-Output
        • 7.2.5.2.2 Address Retry (ARTRY)-Input
    • 7.2.6 Data Bus Arbitration Signals
      • 7.2.6.1 Data Bus Grant (DBG)
        • 7.2.6.1.1 Data Bus Grant (DBG)-Input
        • 7.2.6.1.2 Data Bus Grant (DBG)-Output
      • 7.2.6.2 Data Bus Busy (DBB)
        • 7.2.6.2.1 Data Bus Busy (DBB)-Output
        • 7.2.6.2.2 Data Bus Busy (DBB)-Input
    • 7.2.7 Data Transfer Signals
      • 7.2.7.1 Data Bus (D[0-63])
        • 7.2.7.1.1 Data Bus (D[0-63])-Output
          • Table 7-1. Data Bus Lane Assignments
        • 7.2.7.1.2 Data Bus (D[0-63])-Input
      • 7.2.7.2 Data Bus Parity (DP[0-7])
        • 7.2.7.2.1 Data Bus Parity (DP[0-7])-Output
          • Table 7-2. DP[0-7] Signal Assignments
        • 7.2.7.2.2 Data Bus Parity (DP[0-7])-Input
    • 7.2.8 Data Transfer Termination Signals
      • 7.2.8.1 Transfer Acknowledge (TA)
        • 7.2.8.1.1 Transfer Acknowledge (TA)-Input
        • 7.2.8.1.2 Transfer Acknowledge (TA)-Output
      • 7.2.8.2 Transfer Error Acknowledge (TEA)
        • 7.2.8.2.1 Transfer Error Acknowledge (TEA)-Input
        • 7.2.8.2.2 Transfer Error Acknowledge (TEA)-Output
      • 7.2.8.3 Partial Data Valid Indication (PSDVAL)
        • 7.2.8.3.1 Partial Data Valid (PSDVAL)-Input
        • 7.2.8.3.2 Partial Data Valid (PSDVAL)-Output
• Chapter 8 The 60x Bus
  • 8.1 Terminology
    • Table 8-1. Terminology (continued)
  • 8.2 Bus Configuration
    • 8.2.1 Single-PowerQUICC II Bus Mode
      • Figure 8-1. Single-PowerQUICC II Bus Mode
    • 8.2.2 60x-Compatible Bus Mode
      • Figure 8-2. 60x-Compatible Bus Mode
  • 8.3 60x Bus Protocol Overview
    • Figure 8-3. Basic Transfer Protocol
    • 8.3.1 Arbitration Phase
    • 8.3.2 Address Pipelining and Split-Bus Transactions
  • 8.4 Address Tenure Operations
    • 8.4.1 Address Arbitration
      • Figure 8-4. Address Bus Arbitration with External Bus Master
    • 8.4.2 Address Pipelining
      • Figure 8-5. Address Pipelining
    • 8.4.3 Address Transfer Attribute Signals
      • 8.4.3.1 Transfer Type Signal (TT[0-4]) Encoding
        • Table 8-2. Transfer Type Encoding (continued)
      • 8.4.3.2 Transfer Code Signals TC[0-2]
        • Table 8-3. Transfer Code Encoding for 60x Bus
      • 8.4.3.3 TBST and TSIZ[0-3] Signals and Size of Transfer
        • Table 8-4. Transfer Size Signal Encoding
      • 8.4.3.4 Burst Ordering During Data Transfers
        • Table 8-5. Burst Ordering
      • 8.4.3.5 Effect of Alignment on Data Transfers
        • Table 8-6. Aligned Data Transfers (continued)
        • Table 8-7. Unaligned Data Transfer Example (4-Byte Example) (continued)
      • 8.4.3.6 Effect of Port Size on Data Transfers
        • Figure 8-6. Interface to Different Port Size Devices
        • Table 8-8. Data Bus: Read Cycle Requirements and Write Cycle Content
      • 8.4.3.7 60x-Compatible Bus Mode-Size Calculation
        • Table 8-9. Address and Size State Calculations
      • 8.4.3.8 Extended Transfer Mode
        • Table 8-10. Data Bus Contents for Extended Write Cycles
        • Table 8-11. Data Bus Requirements for Extended Read Cycles
        • Table 8-12. Address and Size State for Extended Transfers (continued)
    • 8.4.4 Address Transfer Termination
      • 8.4.4.1 Address Retried with ARTRY
        • Figure 8-7. Retry Cycle
      • 8.4.4.2 Address Tenure Timing Configuration
    • 8.4.5 Pipeline Control
  • 8.5 Data Tenure Operations
    • 8.5.1 Data Bus Arbitration
    • 8.5.2 Data Streaming Mode
    • 8.5.3 Data Bus Transfers and Normal Termination
      • Figure 8-8. Single-Beat and Burst Data Transfers
    • 8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration
    • 8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
      • Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size
      • Figure 8-10. Burst Transfer to 32-Bit Port Size
    • 8.5.6 Data Bus Termination by Assertion of TEA
      • Figure 8-11. Data Tenure Terminated by Assertion of TEA
  • 8.6 Memory Coherency-MEI Protocol
    • Figure 8-12. MEI Cache Coherency Protocol-State Diagram (WIM = 001)
  • 8.7 Processor State Signals
    • 8.7.1 Support for the lwarx/stwcx. Instruction Pair
    • 8.7.2 TLBISYNC Input
  • 8.8 Little-Endian Mode
• Chapter 9 PCI Bridge
  • Figure 9-1. PCI Bridge in the PowerQUICC II
  • Figure 9-2. PCI Bridge Structure
  • 9.1 Signals
  • 9.2 Clocking
  • 9.3 PCI Bridge Initialization
  • 9.4 SDMA Interface
  • 9.5 Interrupts from PCI Bridge
  • 9.6 60x Bus Arbitration Priority
  • 9.7 60x Bus Masters
  • 9.8 CompactPCI Hot Swap Specification Support
  • 9.9 PCI Interface
    • Table 9-1. PCI Terminology
    • 9.9.1 PCI Interface Operation
      • 9.9.1.1 Bus Commands
        • Table 9-2. PCI Command Definitions
      • 9.9.1.2 PCI Protocol Fundamentals
        • 9.9.1.2.1 Basic Transfer Control
        • 9.9.1.2.2 Addressing
        • 9.9.1.2.3 Byte Enable Signals
        • 9.9.1.2.4 Bus Driving and Turnaround
      • 9.9.1.3 Bus Transactions
        • 9.9.1.3.1 Read and Write Transactions
          • Figure 9-3. Single Beat Read Example
          • Figure 9-4. Burst Read Example
          • Figure 9-5. Single Beat Write Example
          • Figure 9-6. Burst Write Example
        • 9.9.1.3.2 Transaction Termination
          • Figure 9-7. Target-Initiated Terminations
      • 9.9.1.4 Other Bus Operations
        • 9.9.1.4.1 Device Selection
        • 9.9.1.4.2 Fast Back-to-Back Transactions
        • 9.9.1.4.3 Data Streaming
        • 9.9.1.4.4 Host Mode Configuration Access
          • Figure 9-8. PCI Configuration Type 0 Translation (Top = CONFIG_ADDR) (Bottom = PCI Address Lines)
        • 9.9.1.4.5 Agent Mode Configuration Access
        • 9.9.1.4.6 Special Cycle Command
        • 9.9.1.4.7 Interrupt Acknowledge
      • 9.9.1.5 Error Functions
        • 9.9.1.5.1 Parity
        • 9.9.1.5.2 Error Reporting
          • Figure 9-9. PCI Parity Operation
    • 9.9.2 PCI Bus Arbitration
      • 9.9.2.1 Bus Parking
      • 9.9.2.2 Arbitration Algorithm
        • Figure 9-10. PCI Arbitration Example
      • 9.9.2.3 Master Latency Timer
  • 9.10 Address Map
    • Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions
    • Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions
    • Figure 9-13. Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered Transactions
    • Figure 9-14. Address Map Example
    • 9.10.1 Address Map Programming
    • 9.10.2 Address Translation
      • 9.10.2.1 PCI Inbound Translation
        • Figure 9-15. Inbound PCI Memory Address Translation
      • 9.10.2.2 PCI Outbound Translation
        • Figure 9-16. Outbound PCI Memory Address Translation
    • 9.10.3 SIU Registers
  • 9.11 Configuration Registers
    • 9.11.1 Memory-Mapped Configuration Registers
      • Table 9-3. Internal Memory Map (continued)
      • 9.11.1.1 Message Unit (I2O) Registers
      • 9.11.1.2 DMA Controller Registers
      • 9.11.1.3 PCI Outbound Translation Address Registers (POTARx)
        • Figure 9-17. PCI Outbound Translation Address Registers (POTARx)
        • Table 9-4. POTARx Field Descriptions
      • 9.11.1.4 PCI Outbound Base Address Registers (POBARx)
        • Figure 9-18. PCI Outbound Base Address Registers (POBARx)
        • Table 9-5. POBARx Field Descriptions
      • 9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx)
        • Figure 9-19. PCI Outbound Comparison Mask Registers (POCMRx)
        • Table 9-6. POCMRx Field Descriptions
      • 9.11.1.6 Discard Timer Control Register (PTCR)
        • Figure 9-20. Discard Timer Control register (PTCR)
        • Table 9-7. PTCR Field Descriptions
      • 9.11.1.7 General Purpose Control Register (GPCR)
        • Figure 9-21. General Purpose Control Register (GPCR)
        • Table 9-8. GPCR Field Descriptions (continued)
      • 9.11.1.8 PCI General Control Register (PCI_GCR)
        • Figure 9-22. PCI General Control Register (PCI_GCR)
        • Table 9-9. PCI_GCR Field Descriptions
      • 9.11.1.9 Error Status Register (ESR)
        • Figure 9-23. Error Status Register (ESR)
        • Table 9-10. ESR Field Descriptions (continued)
      • 9.11.1.10 Error Mask Register (EMR)
        • Figure 9-24. Error Mask Register (EMR)
        • Table 9-11. EMR Field Descriptions (continued)
      • 9.11.1.11 Error Control Register (ECR)
        • Figure 9-25. Error Control Register (ECR)
        • Table 9-12. ECR Field Descriptions
      • 9.11.1.12 PCI Error Address Capture Register (PCI_EACR)
        • Figure 9-26. PCI Error Address Capture Register (PCI_EACR)
        • Table 9-13. PCI_EACR Field Descriptions
      • 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR)
        • Figure 9-27. PCI Error Data Capture Register (PCI_EDCR)
        • Table 9-14. PCI_EDCR Field Description
      • 9.11.1.14 PCI Error Control Capture Register (PCI_ECCR)
        • Figure 9-28. PCI Error Control Capture Register (PCI_ECCR)
        • Table 9-15. PCI_ECCR Field Descriptions (continued)
      • 9.11.1.15 PCI Inbound Translation Address Registers (PITARx)
        • Figure 9-29. PCI Inbound Translation Address Registers (PITARx)
        • Table 9-16. PITARx Field Descriptions
      • 9.11.1.16 PCI Inbound Base Address Registers (PIBARx)
        • Figure 9-30. PCI Inbound Base Address Registers (PIBARx)
      • 9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx)
        • Table 9-17. PIBARx Field Descriptions
        • Figure 9-31. PCI Inbound Comparison Mask Registers (PICMRx)
        • Table 9-18. PICMRx Field Descriptions
    • 9.11.2 PCI Bridge Configuration Registers
      • Table 9-19. PCI Bridge PCI Configuration Registers (continued)
      • Figure 9-32. PCI Bridge PCI Configuration Registers
      • 9.11.2.1 Vendor ID Register
        • Figure 9-33. Vendor ID Register
        • Table 9-20. Vendor ID Register Description
      • 9.11.2.2 Device ID Register
        • Figure 9-34. Device ID Register
        • Table 9-21. Device ID Register Description
      • 9.11.2.3 PCI Bus Command Register
        • Figure 9-35. PCI Bus Command Register
        • Table 9-22. PCI Bus Command Register Description
      • 9.11.2.4 PCI Bus Status Register
        • Figure 9-36. PCI Bus Status Register
        • Table 9-23. PCI Bus Status Register Description
      • 9.11.2.5 Revision ID Register
        • Figure 9-37. Revision ID Register
        • Table 9-24. Revision ID Register Description
      • 9.11.2.6 PCI Bus Programming Interface Register
        • Figure 9-38. PCI Bus Programming Interface Register
        • Table 9-25. PCI Bus Programming Interface Register Description
      • 9.11.2.7 Subclass Code Register
        • Figure 9-39. Subclass Code Register
        • Table 9-26. Subclass Code Register Description
      • 9.11.2.8 PCI Bus Base Class Code Register
        • Figure 9-40. PCI Bus Base Class Code Register
        • Table 9-27. PCI Bus Base Class Code Register Description
      • 9.11.2.9 PCI Bus Cache Line Size Register
        • Figure 9-41. PCI Bus Cache Line Size Register
        • Table 9-28. PCI Bus Cache Line Size Register Description
      • 9.11.2.10 PCI Bus Latency Timer Register
        • Figure 9-42. PCI Bus Latency Timer Register
        • Table 9-29. PCI Bus Latency Timer Register Description
      • 9.11.2.11 Header Type Register
        • Figure 9-43. Header Type Register
        • Table 9-30. Header Type Register Description
      • 9.11.2.12 BIST Control Register
        • Figure 9-44. BIST Control Register
        • Table 9-31. BIST Control Register Description
      • 9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
        • Figure 9-45. PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
        • Table 9-32. PIMMRBAR Field Descriptions
      • 9.11.2.14 General Purpose Local Access Base Address Registers (GPLABARx)
        • Figure 9-46. General Purpose Local Access Base Address Registers (GPLABARx)
        • Table 9-33. GPLABARx Field Descriptions
      • 9.11.2.15 Subsystem Vendor ID Register
        • Figure 9-47. Subsystem Vendor ID Register
        • Table 9-34. Subsystem Vendor ID Register Description
      • 9.11.2.16 Subsystem Device ID Register
        • Figure 9-48. Subsystem Device ID Register
        • Table 9-35. Subsystem Device ID Description Register
      • 9.11.2.17 PCI Bus Capabilities Pointer Register
        • Figure 9-49. PCI Bus Capabilities Pointer Register
        • Table 9-36. PCI Bus Capabilities Pointer Register Description
      • 9.11.2.18 PCI Bus Interrupt Line Register
        • Figure 9-50. PCI Bus Interrupt Line Register
        • Table 9-37. PCI Bus Interrupt Line Register Description
      • 9.11.2.19 PCI Bus Interrupt Pin Register
        • Figure 9-51. PCI Bus Interrupt Pin Register
        • Table 9-38. PCI Bus Interrupt Pin Register Description
      • 9.11.2.20 PCI Bus MIN GNT
        • Figure 9-52. PCI Bus MIN GNT
        • Table 9-39. PCI Bus MIN GNT Description
      • 9.11.2.21 PCI Bus MAX LAT
        • Figure 9-53. PCI Bus MAX LAT
        • Table 9-40. PCI Bus MAX LAT Description
      • 9.11.2.22 PCI Bus Function Register
        • Figure 9-54. PCI Bus Function Register
        • Table 9-41. PCI Bus Function Register Field Descriptions
      • 9.11.2.23 PCI Bus Arbiter Configuration Register
        • Figure 9-55. PCI Bus Arbiter Configuration Register
        • Table 9-42. PCI Bus Arbiter Configuration Register Field Description
      • 9.11.2.24 PCI Hot Swap Register Block
        • Figure 9-56. Hot Swap Register Block
        • Table 9-43. Hot Swap Register Block Field Descriptions
      • 9.11.2.25 PCI Hot Swap Control Status Register
        • Figure 9-57. Hot Swap Control Status Register
        • Table 9-44. Hot Swap Control Status Register Field Descriptions
      • 9.11.2.26 PCI Configuration Register Access from the Core
      • 9.11.2.27 PCI Configuration Register Access in Big-Endian Mode
        • 9.11.2.27.1 Additional Information on Endianess
        • 9.11.2.27.2 Notes on GPCR[LE_MODE]
      • 9.11.2.28 Initializing the PCI Configuration Registers
        • Figure 9-58. Data Structure for Register Initialization
        • Table 9-45. Bit Settings for Register Initialization Data Structure
        • Figure 9-59. PCI Configuration Data Structure for the EEPROM
  • 9.12 Message Unit (I2O)
    • 9.12.1 Message Registers
      • 9.12.1.1 Inbound Message Registers (IMRx)
        • Figure 9-60. Inbound Message Registers (IMRx)
        • Table 9-46. IMRx Field Descriptions
      • 9.12.1.2 Outbound Message Registers (OMRx)
        • Figure 9-61. Outbound Message Registers (OMRx)
        • Table 9-47. OMRx Field Descriptions
    • 9.12.2 Door Bell Registers
      • 9.12.2.1 Outbound Doorbell Register (ODR)
        • Figure 9-62. Outbound Doorbell Register (ODR)
        • Table 9-48. ODR Field Descriptions
      • 9.12.2.2 Inbound Doorbell Register (IDR)
        • Figure 9-63. Inbound Doorbell Register (IDR)
        • Table 9-49. IDR Field Descriptions
    • 9.12.3 I2O Unit
      • Figure 9-64. I2O Message Queue
      • 9.12.3.1 PCI Configuration Identification
      • 9.12.3.2 Inbound FIFOs
        • 9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound Free_FIFO Tail Pointer Register (IFTPR)
          • Figure 9-65. Inbound Free_FIFO Head Pointer Register (IFHPR)
          • Table 9-50. IFHPR Field Descriptions
          • Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTPR)
          • Table 9-51. IFTPR Field Descriptions
        • 9.12.3.2.2 Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound Post_FIFO Tail Pointer Register (IPTPR)
          • Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHPR)
          • Table 9-52. IPHPR Field Descriptions
          • Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR)
          • Table 9-53. IPTPR Field Descriptions
      • 9.12.3.3 Outbound FIFOs
        • 9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound Free_FIFO Tail Pointer Register (OFTPR)
          • Figure 9-69. Outbound Free_FIFO Head Pointer Register (OFHPR)
          • Table 9-54. OFHPR Field Descriptions
          • Figure 9-70. Outbound Free_FIFO Tail Pointer Register (OFTPR)
          • Table 9-55. OFTPR Field Descriptions
        • 9.12.3.3.2 Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound Post_FIFO Tail Pointer Register (OPTPR)
          • Figure 9-71. Outbound Post_FIFO Head Pointer Register (OPHPR)
          • Table 9-56. OPHPR Field Descriptions
          • Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPTPR)
          • Table 9-57. OPTPR Field Descriptions
      • 9.12.3.4 I2O Registers
        • 9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR)
          • Figure 9-73. Inbound FIFO Queue Port Register (IFQPR)
          • Table 9-58. IFQPR Field Descriptions
        • 9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR)
          • Figure 9-74. Outbound FIFO Queue Port Register (OFQPR)
          • Table 9-59. OFQPR Field Descriptions
        • 9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR)
          • Figure 9-75. Outbound Message Interrupt Status Register (OMISR)
          • Table 9-60. OMISR Field Descriptions
        • 9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR)
          • Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR)
          • Table 9-61. OMIMR Field Descriptions
        • 9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR)
          • Figure 9-77. Inbound Message Interrupt Status Register (IMISR)
          • Table 9-62. IMISR Field Descriptions
        • 9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR)
          • Figure 9-78. Inbound Message Interrupt Mask Register (IMIMR)
          • Table 9-63. IMIMR Field Descriptions (continued)
        • 9.12.3.4.7 Messaging Unit Control Register (MUCR)
          • Figure 9-79. Messaging Unit Control Register (MUCR)
          • Table 9-64. MUCR Field Descriptions
        • 9.12.3.4.8 Queue Base Address Register (QBAR)
          • Figure 9-80. Queue Base Address Register (QBAR)
          • Table 9-65. QBAR Field Descriptions
  • 9.13 DMA Controller
    • Figure 9-81. DMA Controller Block Diagram
    • 9.13.1 DMA Operation
      • 9.13.1.1 DMA Direct Mode
      • 9.13.1.2 DMA Chaining Mode
      • 9.13.1.3 DMA Coherency
      • 9.13.1.4 Halt and Error Conditions
      • 9.13.1.5 DMA Transfer Types
      • 9.13.1.6 DMA Registers
        • 9.13.1.6.1 DMA Mode Register [0-3] (DMAMRx)
          • Figure 9-82. DMA Mode Register [0-3] (DMAMRx)
          • Table 9-66. DMAMRx Field Descriptions (continued)
        • 9.13.1.6.2 DMA Status Register [0-3] (DMASRx)
          • Figure 9-83. DMA Status Register [0-3] (DMASRx)
          • Table 9-67. DMASRx Field Descriptions
        • 9.13.1.6.3 DMA Current Descriptor Address Register [0-3] (DMACDARx)
          • Figure 9-84. DMA Current Descriptor Address Register [0-3] (DMACDARx)
          • Table 9-68. DMACDARx Field Descriptions
        • 9.13.1.6.4 DMA Source Address Register [0-3] (DMASARx)
          • Figure 9-85. DMA Source Address Register [0-3] (DMASARx)
          • Table 9-69. DMASARx Field Descriptions
        • 9.13.1.6.5 DMA Destination Address Register [0-3] (DMADARx)
          • Figure 9-86. DMA Destination Address Register [0-3] (DMADARx)
          • Table 9-70. DMADARx Field Descriptions
        • 9.13.1.6.6 DMA Byte Count Register [0-3] (DMABCRx)
          • Figure 9-87. DMA Byte Count Register [0-3] (DMABCRx)
          • Table 9-71. DMABCRx Field Descriptions
        • 9.13.1.6.7 DMA Next Descriptor Address Register [0-3] (DMANDARx)
          • Figure 9-88. DMA Next Descriptor Address Register [0-3] (DMANDARx)
          • Table 9-72. DMANDARx Field Descriptions
    • 9.13.2 DMA Segment Descriptors
      • Table 9-73. DMA Segment Descriptor Fields
      • Figure 9-89. DMA Chain of Segment Descriptors
      • 9.13.2.1 Descriptor in Big Endian Mode
      • 9.13.2.2 Descriptor in Little Endian Mode
  • 9.14 Error Handling
    • 9.14.1 Interrupt and Error Signals
      • 9.14.1.1 PCI Bus Error Signals
        • 9.14.1.1.1 System Error (SERR)
        • 9.14.1.1.2 Parity Error (PERR)
        • 9.14.1.1.3 Error Reporting
      • 9.14.1.2 Illegal Register Access Error
      • 9.14.1.3 PCI Interface
        • 9.14.1.3.1 Address Parity Error
        • 9.14.1.3.2 Data Parity Error
        • 9.14.1.3.3 Master-Abort Transaction Termination
        • 9.14.1.3.4 Target-Abort Error
        • 9.14.1.3.5 NMI
      • 9.14.1.4 Embedded Utilities
        • 9.14.1.4.1 Outbound Free Queue Overflow
        • 9.14.1.4.2 Inbound Post Queue Overflow
        • 9.14.1.4.3 Inbound DoorBell Machine Check
• Chapter 10 Clocks and Power Control
  • 10.1 Clock Unit
  • 10.2 Clock Configuration
  • 10.3 External Clock Inputs
  • 10.4 Main PLL
    • 10.4.1 PLL Block Diagram
      • Figure 10-1. System PLL Block Diagram
    • 10.4.2 Skew Elimination
    • 10.4.3 PCI Bridge Clocking
      • 10.4.3.1 PCI Bridge as an Agent Operating from the PCI System Clock
        • Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock
      • 10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock
        • Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock
        • 10.4.3.2.1 CPM CLOCK and PCI Frequency Equations
  • 10.5 Clock Dividers
  • 10.6 PowerQUICC II Internal Clock Signals
    • 10.6.1 General System Clocks
  • 10.7 PLL Pins
    • Table 10-1. Dedicated PLL Pins (continued)
    • Figure 10-4. PLL Filtering Circuit
  • 10.8 System Clock Control Register (SCCR)
    • Figure 10-5. System Clock Control Register (SCCR)
    • Table 10-2. SCCR Field Descriptions (continued)
  • 10.9 System Clock Mode Register (SCMR)
    • Figure 10-6. System Clock Mode Register (SCMR)
    • Table 10-3. SCMR Field Descriptions
    • Figure 10-7. Relationships of SCMR Parameters
    • Table 10-4. 60x Bus-to-Core Frequency
  • 10.10 Basic Power Structure
• Chapter 11 Memory Controller
  • Figure 11-1. Dual-Bus Architecture
  • 11.1 Features
  • 11.2 Basic Architecture
    • Figure 11-2. Memory Controller Machine Selection
    • Figure 11-3. Simple System Configuration
    • Figure 11-4. Basic Memory Controller Operation
    • 11.2.1 Address and Address Space Checking
    • 11.2.2 Page Hit Checking
    • 11.2.3 Error Checking and Correction (ECC)
    • 11.2.4 Parity Generation and Checking
    • 11.2.5 Transfer Error Acknowledge (TEA) Generation
    • 11.2.6 Machine Check Interrupt (MCP) Generation
    • 11.2.7 Data Buffer Controls (BCTLx and LWR)
    • 11.2.8 Atomic Bus Operation
    • 11.2.9 Data Pipelining
    • 11.2.10 External Memory Controller Support
    • 11.2.11 External Address Latch Enable Signal (ALE)
    • 11.2.12 ECC/Parity Byte Select (PBSE)
    • 11.2.13 Partial Data Valid Indication (PSDVAL)
      • Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion
      • Figure 11-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer
    • 11.2.14 BADDR[27:31] Signal Connections
      • Table 11-2. BADDR Connections
  • 11.3 Register Descriptions
    • Table 11-3. 60x Bus Memory Controller Registers
    • 11.3.1 Base Registers (BRx)
      • Figure 11-6. Base Registers (BRx)
      • Table 11-4. BRx Field Descriptions (continued)
    • 11.3.2 Option Registers (ORx)
      • Figure 11-7. Option Registers (ORx)-SDRAM Mode
      • Table 11-5. ORx Field Descriptions (SDRAM Mode) (continued)
      • Figure 11-8. ORx -GPCM Mode
      • Table 11-6. ORx-GPCM Mode Field Descriptions (continued)
      • Figure 11-9. ORx-UPM Mode
      • Table 11-7. Option Register (ORx)-UPM Mode
    • 11.3.3 60x SDRAM Mode Register (PSDMR)
      • Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)
      • Table 11-8. PSDMR Field Descriptions (continued)
    • 11.3.4 Local Bus SDRAM Mode Register (LSDMR)
      • Table 11-9. LSDMR Field Descriptions (continued)
    • 11.3.5 Machine A/B/C Mode Registers (MxMR)
      • Figure 11-11. Machine x Mode Registers (MxMR)
      • Table 11-10. Machine x Mode Registers (MxMR) (continued)
    • 11.3.6 Memory Data Register (MDR)
      • Figure 11-12. Memory Data Register (MDR)
      • Table 11-11. MDR Field Descriptions
    • 11.3.7 Memory Address Register (MAR)
      • Figure 11-13. Memory Address Register (MAR)
      • Table 11-12. MAR Field Description
    • 11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
      • Figure 11-14. 60x Bus-Assigned UPM Refresh Timer (PURT)
      • Table 11-13. 60x Bus-Assigned UPM Refresh Timer (PURT)
    • 11.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
      • Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT)
      • Table 11-14. Local Bus-Assigned UPM Refresh Timer (LURT)
    • 11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
      • Figure 11-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
      • Table 11-15. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
    • 11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
      • Figure 11-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT)
      • Table 11-16. LSRT Field Descriptions
    • 11.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
      • Figure 11-18. Memory Refresh Timer Prescaler Register (MPTPR)
      • Table 11-17. MPTPR Field Descriptions
    • 11.3.13 60x Bus Error Status and Control Registers (TESCRx)
    • 11.3.14 Local Bus Error Status and Control Registers (L_TESCRx)
  • 11.4 SDRAM Machine
    • Table 11-18. SDRAM Interface Signals
    • Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)
    • 11.4.1 Supported SDRAM Configurations
    • 11.4.2 SDRAM Power-On Initialization
    • 11.4.3 JEDEC-Standard SDRAM Interface Commands
      • Table 11-19. SDRAM Interface Commands
    • 11.4.4 Page-Mode Support and Pipeline Accesses
    • 11.4.5 Bank Interleaving
      • 11.4.5.1 Using BNKSEL Signals in Single-PowerQUICC II Bus Mode
      • 11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)
        • Table 11-20. SDRAM Address Multiplexing (A0-A15)
        • Table 11-21. SDRAM Address Multiplexing (A16-A31)
    • 11.4.6 SDRAM Device-Specific Parameters
      • 11.4.6.1 Precharge-to-Activate Interval
        • Figure 11-20. PRETOACT = 2 (2 Clock Cycles)
      • 11.4.6.2 Activate to Read/Write Interval
        • Figure 11-21. ACTTORW = 2 (2 Clock Cycles)
      • 11.4.6.3 Column Address to First Data Out-CAS Latency
        • Figure 11-22. CL = 2 (2 Clock Cycles)
      • 11.4.6.4 Last Data Out to Precharge
        • Figure 11-23. LDOTOPRE = 2 (-2 Clock Cycles)
      • 11.4.6.5 Last Data In to Precharge-Write Recovery
        • Figure 11-24. WRC = 2 (2 Clock Cycles)
      • 11.4.6.6 Refresh Recovery Interval (RFRC)
        • Figure 11-25. RFRC = 4 (6 Clock Cycles)
      • 11.4.6.7 External Address Multiplexing Signal
        • Figure 11-26. EAMUX = 1
      • 11.4.6.8 External Address and Command Buffers (BUFCMD)
        • Figure 11-27. BUFCMD = 1
    • 11.4.7 SDRAM Interface Timing
      • Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3
      • Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3
      • Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
      • Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
      • Figure 11-32. SDRAM Single-Beat Write, Page Hit
      • Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed
      • Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3
      • Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit
      • Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit
    • 11.4.8 SDRAM Read/Write Transactions
    • 11.4.9 SDRAM Mode-Set Command Timing
      • Figure 11-37. SDRAM Mode-Set Command Timing
      • Figure 11-38. Mode Data Bit Settings
    • 11.4.10 SDRAM Refresh
    • 11.4.11 SDRAM Refresh Timing
      • Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing
    • 11.4.12 SDRAM Configuration Examples
      • 11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)
        • Table 11-22. 60x Address Bus Partition
        • Table 11-23. SDRAM Device Address Port during activate Command
        • Table 11-24. SDRAM Device Address Port during read/write Command
        • Table 11-25. Register Settings (Page-Based Interleaving)
    • 11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)
      • Table 11-26. 60x Address Bus Partition
      • Table 11-27. SDRAM Device Address Port during activate Command
      • Table 11-28. SDRAM Device Address Port during read/write Command
      • Table 11-29. Register Settings (Bank-Based Interleaving)
  • 11.5 General-Purpose Chip-Select Machine (GPCM)
    • Table 11-30. GPCM Interfaces Signals
    • Figure 11-40. GPCM-to-SRAM Configuration
    • 11.5.1 Timing Configuration
      • Table 11-31. GPCM Strobe Signal Behavior
      • 11.5.1.1 Chip-Select Assertion Timing
        • Figure 11-41. GPCM Peripheral Device Interface
        • Figure 11-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)
      • 11.5.1.2 Chip-Select and Write Enable Deassertion Timing
        • Figure 11-43. GPCM Memory Device Interface
        • Figure 11-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)
        • Figure 11-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0)
      • 11.5.1.3 Relaxed Timing
        • Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
        • Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)
        • Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)
        • Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)
      • 11.5.1.4 Output Enable (OE) Timing
      • 11.5.1.5 Programmable Wait State Configuration
      • 11.5.1.6 Extended Hold Time on Read Accesses
        • Table 11-32. TRLX and EHTR Combinations
        • Figure 11-50. GPCM Read Followed by Read (ORx[29-30] = 00, Fastest Timing)
        • Figure 11-51. GPCM Read Followed by Read (ORx[29-30] = 01)
        • Figure 11-52. GPCM Read Followed by Write (ORx[29-30] = 01)
        • Figure 11-53. GPCM Read Followed by Write (ORx[29-30] = 10)
    • 11.5.2 External Access Termination
      • Figure 11-54. External Termination of GPCM Access
    • 11.5.3 Boot Chip-Select Operation
      • Table 11-33. . Boot Bank Field Values after Reset (continued)
    • 11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM
  • 11.6 User-Programmable Machines (UPMs)
    • Table 11-34. UPM Interfaces Signals
    • Figure 11-55. User-Programmable Machine Block Diagram
    • 11.6.1 Requests
      • Figure 11-56. RAM Array Indexing
      • Table 11-35. UPM Routines Start Addresses
      • 11.6.1.1 Memory Access Requests
      • 11.6.1.2 UPM Refresh Timer Requests
        • Figure 11-57. Memory Refresh Timer Request Block Diagram
      • 11.6.1.3 Software Requests-run Command
      • 11.6.1.4 Exception Requests
    • 11.6.2 Programming the UPMs
    • 11.6.3 Clock Timing
      • Figure 11-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios
      • Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios
      • Figure 11-60. UPM Signals Timing Example
    • 11.6.4 The RAM Array
      • Figure 11-61. RAM Array and Signal Generation
      • 11.6.4.1 RAM Words
        • Figure 11-62. The RAM Word
        • Table 11-36. RAM Word Bit Settings (continued)
        • 11.6.4.1.1 Chip-Select Signals (CxTx)
          • Figure 11-63. CS Signal Selection
        • 11.6.4.1.2 Byte-Select Signals (BxTx)
          • Figure 11-64. BS Signal Selection
        • 11.6.4.1.3 General-Purpose Signals (GxTx, GOx)
        • 11.6.4.1.4 Loop Control
          • Table 11-37. MxMR Loop Field Usage
        • 11.6.4.1.5 Repeat Execution of Current RAM Word (REDO)
      • 11.6.4.2 Address Multiplexing
        • Table 11-38. UPM Address Multiplexing
      • 11.6.4.3 Data Valid and Data Sample Control
        • Figure 11-65. UPM Read Access Data Sampling
      • 11.6.4.4 Signals Negation
      • 11.6.4.5 The Wait Mechanism
        • Figure 11-66. Wait Mechanism Timing for Internal and External Synchronous Masters
      • 11.6.4.6 Extended Hold Time on Read Accesses
    • 11.6.5 UPM DRAM Configuration Example
      • Table 11-39. 60x Address Bus Partition
      • Table 11-40. DRAM Device Address Port during an activate command
      • Table 11-41. Register Settings
    • 11.6.6 Differences between MPC8xx UPM and MPC82xx UPM
  • 11.7 Memory System Interface Example Using UPM
    • Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
    • Table 11-42. UPMs Attributes Example
    • Figure 11-68. Single-Beat Read Access to FPM DRAM
    • Figure 11-69. Single-Beat Write Access to FPM DRAM
    • Figure 11-70. Burst Read Access to FPM DRAM (No LOOP)
    • Figure 11-71. Burst Read Access to FPM DRAM (LOOP)
    • Figure 11-72. Burst Write Access to FPM DRAM (No LOOP)
    • Figure 11-73. Refresh Cycle (CBR) to FPM DRAM
    • Figure 11-74. Exception Cycle
    • Table 11-43. UPMs Attributes Example
    • Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)
    • 11.7.0.1 EDO Interface Example
      • Figure 11-76. PowerQUICC II/EDO Interface Connection to the 60x Bus
      • Table 11-44. EDO Connection Field Value Example (continued)
      • Figure 11-77. Single-Beat Read Access to EDO DRAM
      • Figure 11-78. Single-Beat Write Access to EDO DRAM
      • Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States
      • Figure 11-80. Burst Read Access to EDO DRAM
      • Figure 11-81. Burst Write Access to EDO DRAM
      • Figure 11-82. Refresh Cycle (CBR) to EDO DRAM
      • Figure 11-83. Exception Cycle For EDO DRAM
  • 11.8 Handling Devices with Slow or Variable Access Times
    • 11.8.1 Hierarchical Bus Interface Example
    • 11.8.2 Slow Devices Example
  • 11.9 External Master Support (60x-Compatible Mode)
    • 11.9.1 60x-Compatible External Masters (non-PowerQUICC II)
    • 11.9.2 PowerQUICC II External Masters
    • 11.9.3 Extended Controls in 60x-Compatible Mode
    • 11.9.4 Address Incrementing for External Bursting Masters
    • 11.9.5 External Masters Timing
      • Figure 11-84. Pipelined Bus Operation and Memory Access in 60x-Compatible Mode
      • Figure 11-85. External Master Access (GPCM)
      • 11.9.5.1 Example of External Master Using the SDRAM Machine
        • Figure 11-86. External Master Configuration with SDRAM Device
• Chapter 12 Secondary (L2) Cache Support
  • 12.1 L2 Cache Configurations
    • 12.1.1 Copy-Back Mode
      • Figure 12-1. L2 Cache in Copy-Back Mode
    • 12.1.2 Write-Through Mode
      • Figure 12-2. External L2 Cache in Write-Through Mode
    • 12.1.3 ECC/Parity Mode
      • Figure 12-3. External L2 Cache in ECC/Parity Mode
  • 12.2 L2 Cache Interface Parameters
  • 12.3 System Requirements When Using the L2 Cache Interface
  • 12.4 L2 Cache Operation
  • 12.5 Timing Example
    • Figure 12-4. Read Access with L2 Cache
• Chapter 13 IEEE 1149.1 Test Access Port
  • 13.1 Overview
    • Figure 13-1. Test Logic Block Diagram
    • Table 13-1. TAP Signals
  • 13.2 TAP Controller
    • Figure 13-2. TAP Controller State Machine
  • 13.3 Boundary Scan Register
    • Figure 13-3. Output Pin Cell (O.Pin)
    • Figure 13-4. Observe-Only Input Pin Cell (I.Obs)
    • Figure 13-5. Output Control Cell (IO.CTL)
    • Figure 13-6. General Arrangement of Bidirectional Pin Cells
  • 13.4 Instruction Register
    • Table 13-2. Instruction Decoding (continued)
  • 13.5 PowerQUICC II Restrictions
  • 13.6 Nonscan Chain Operation
• Part IV Communications Processor Module
  • Intended Audience
  • Contents
  • Suggested Reading
  • Architecture Documentation
  • Conventions
  • Acronyms and Abbreviations
• Chapter 14 Communications Processor Module Overview
  • 14.1 Features
    • Figure 14-1. PowerQUICC II CPM Block Diagram
  • 14.2 PowerQUICC II Serial Configurations
    • Table 14-1. Possible PowerQUICC II Applications
  • 14.3 Communications Processor (CP)
    • 14.3.1 CPM Performance Evaluation
    • 14.3.2 Features
    • 14.3.3 CP Block Diagram
      • Figure 14-2. Communications Processor (CP) Block Diagram
    • 14.3.4 G2 Core Interface
    • 14.3.5 Peripheral Interface
      • Table 14-2. Peripheral Prioritization (continued)
    • 14.3.6 Execution from RAM
    • 14.3.7 RISC Controller Configuration Register (RCCR)
      • Figure 14-3. RISC Controller Configuration Register (RCCR
      • Table 14-3. RISC Controller Configuration Register Field Descriptions (continued)
    • 14.3.8 RISC Time-Stamp Control Register (RTSCR)
      • Figure 14-4. RISC Time-Stamp Control Register (RTSCR)
      • Table 14-4. RTSCR Field Descriptions
    • 14.3.9 RISC Time-Stamp Register (RTSR)
      • Figure 14-5. RISC Time-Stamp Register (RTSR)
    • 14.3.10 RISC Microcode Revision Number
      • Table 14-5. RISC Microcode Revision Number
  • 14.4 Command Set
    • 14.4.1 CP Command Register (CPCR)
      • Figure 14-6. CP Command Register (CPCR)
      • Table 14-6. CP Command Register Field Descriptions (continued)
      • 14.4.1.1 CP Commands
        • Table 14-7. CP Command Opcodes
        • Table 14-8. Command Descriptions (continued)
    • 14.4.2 Command Register Example
    • 14.4.3 Command Execution Latency
  • 14.5 Dual-Port RAM
    • Figure 14-7. Dual-Port RAM Block Diagram
    • Figure 14-8. Dual-Port RAM Memory Map
    • 14.5.1 Buffer Descriptors (BDs)
      • Table 14-9. Buffer Descriptor Format
    • 14.5.2 Parameter RAM
      • Table 14-10. Parameter RAM
  • 14.6 RISC Timer Tables
    • 14.6.1 RISC Timer Table Parameter RAM
      • Figure 14-9. RISC Timer Table RAM Usage
      • Table 14-11. RISC Timer Table Parameter RAM
    • 14.6.2 RISC Timer Command Register (TM_CMD)
      • Figure 14-10. RISC Timer Command Register (TM_CMD)
      • Table 14-12. TM_CMD Field Descriptions
    • 14.6.3 RISC Timer Table Entries
    • 14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
      • Figure 14-11. RISC Timer Event Register (RTER)/Mask Register (RTMR)
    • 14.6.5 set timer Command
    • 14.6.6 RISC Timer Initialization Sequence
    • 14.6.7 RISC Timer Initialization Example
    • 14.6.8 RISC Timer Interrupt Handling
    • 14.6.9 RISC Timer Table Scan Algorithm
    • 14.6.10 Using the RISC Timers to Track CP Loading
• Chapter 15 Serial Interface with Time-Slot Assigner
  • Figure 15-1. SI Block Diagram
  • 15.1 Features
  • 15.2 Overview
    • Figure 15-2. Various Configurations of a Single TDM Channel
    • Figure 15-3. Dual TDM Channel Example
  • 15.3 Enabling Connections to TSA
    • Figure 15-4. Enabling Connections to the TSA
  • 15.4 Serial Interface RAM
    • 15.4.1 One Multiplexed Channel with Static Frames
      • Figure 15-5. One TDM Channel with Static Frames and Independent Rx and Tx Routes
    • 15.4.2 One Multiplexed Channel with Dynamic Frames
      • Figure 15-6. One TDM Channel with Shadow RAM for Dynamic Route Change
    • 15.4.3 Programming SIx RAM Entries
      • Figure 15-7. SIx RAM Entry Fields
      • Table 15-1. SIx RAM Entry (MCC = 0) (continued)
      • Figure 15-8. Using the SWTR Feature
      • Table 15-2. SIx RAM Entry (MCC = 1)
    • 15.4.4 SIx RAM Programming Example
      • Table 15-3. SIx RAM Entry Descriptions
    • 15.4.5 Static and Dynamic Routing
      • Figure 15-9. Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size
  • 15.5 Serial Interface Registers
    • 15.5.1 SI Global Mode Registers (SIxGMR)
      • Figure 15-10. SI Global Mode Registers (SIxGMR)
      • Table 15-4. SIxGMR Field Descriptions
    • 15.5.2 SI Mode Registers (SIxMR)
      • Figure 15-11. SI Mode Registers (SIxMR)
      • Table 15-5. SIxMR Field Descriptions (continued)
      • Figure 15-12. One-Clock Delay from Sync to Data (xFSD = 01)
      • Figure 15-13. No Delay from Sync to Data (xFSD = 00)
      • Figure 15-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01
      • Figure 15-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01
      • Figure 15-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00
      • Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
    • 15.5.3 SIx RAM Shadow Address Registers (SIxRSR)
      • Figure 15-18. SIx RAM Shadow Address Registers (SIxRSR)
      • Table 15-6. SIxRSR Field Descriptions
    • 15.5.4 SI Command Register (SIxCMDR)
      • Figure 15-19. SI Command Register (SIxCMDR)
      • Table 15-7. SIxCMDR Field Description
    • 15.5.5 SI Status Registers (SIxSTR)
      • Figure 15-20. SI Status Registers (SIxSTR)
      • Table 15-8. SIxSTR Field Descriptions
  • 15.6 Serial Interface IDL Interface Support
    • Figure 15-21. Dual IDL Bus Application Example
    • 15.6.1 IDL Interface Example
      • Figure 15-22. IDL Terminal Adaptor
      • Table 15-9. IDL Signal Descriptions
      • Figure 15-23. IDL Bus Signals
    • 15.6.2 IDL Interface Programming
      • Table 15-10. SIx RAM Entries for an IDL Interface (continued)
  • 15.7 Serial Interface GCI Support
    • Table 15-11. GCI Signals
    • Figure 15-24. GCI Bus Signals
    • 15.7.1 SI GCI Activation/Deactivation Procedure
    • 15.7.2 Serial Interface GCI Programming
      • 15.7.2.1 Normal Mode GCI Programming
      • 15.7.2.2 SCIT Programming
        • Table 15-12. SIx RAM Entries for a GCI Interface (SCIT Mode)
• Chapter 16 CPM Multiplexing
  • Figure 16-1. CPM Multiplexing Logic (CMX) Block Diagram
  • 16.1 Features
  • 16.2 Enabling Connections to TSA or NMSI
    • Figure 16-2. Enabling Connections to the TSA
  • 16.3 NMSI Configuration
    • Figure 16-3. Bank of Clocks
    • Table 16-1. Clock Source Options
  • 16.4 CMX Registers
    • 16.4.1 CMX UTOPIA Address Register (CMXUAR)
      • Figure 16-4. CMX UTOPIA Address Register (CMXUAR)
      • Table 16-2. CMXUAR Field Descriptions (continued)
      • Figure 16-5. Connection of the Master Address
      • Figure 16-6. Connection of the Slave Address
      • Figure 16-7. Multi-PHY Receive Address Multiplexing
    • 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)
      • Figure 16-8. CMX SI1 Clock Route Register (CMXSI1CR)
      • Table 16-3. CMXSI1CR Field Descriptions
    • 16.4.3 CMX SI2 Clock Route Register (CMXSI2CR)
      • Figure 16-9. CMX SI2 Clock Route Register (CMXSI2CR)
      • Table 16-4. CMXSI2CR Field Descriptions
    • 16.4.4 CMX FCC Clock Route Register (CMXFCR)
      • Figure 16-10. CMX FCC Clock Route Register (CMXFCR)
      • Table 16-5. CMXFCR Field Descriptions (continued)
    • 16.4.5 CMX SCC Clock Route Register (CMXSCR)
      • Figure 16-11. CMX SCC Clock Route Register (CMXSCR)
      • Table 16-6. CMXSCR Field Descriptions (continued)
    • 16.4.6 CMX SMC Clock Route Register (CMXSMR)
      • Figure 16-12. CMX SMC Clock Route Register (CMXSMR)
      • Table 16-7. CMXSMR Field Descriptions
• Chapter 17 Baud-Rate Generators (BRGs)
  • Figure 17-1. Baud-Rate Generator (BRG) Block Diagram
  • 17.1 BRG Configuration Registers 1-8 (BRGCx)
    • Figure 17-2. Baud-Rate Generator Configuration Registers (BRGCx)
    • Table 17-1. BRGCx Field Descriptions
    • Table 17-2. BRG External Clock Source Options
  • 17.2 Autobaud Operation on a UART
  • 17.3 UART Baud Rate Examples
    • Table 17-3. Typical Baud Rates for Asynchronous Communication
• Chapter 18 Timers
  • Figure 18-1. Timer Block Diagram
  • 18.1 Features
  • 18.2 General-Purpose Timer Units
    • 18.2.1 Cascaded Mode
      • Figure 18-2. Timer Cascaded Mode Block Diagram
    • 18.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)
      • Figure 18-3. Timer Global Configuration Register 1 (TGCR1)
      • Table 18-1. TGCR1 Field Descriptions
      • Figure 18-4. Timer Global Configuration Register 2 (TGCR2)
      • Table 18-2. TGCR2 Field Descriptions
    • 18.2.3 Timer Mode Registers (TMR1-TMR4)
      • Figure 18-5. Timer Mode Registers (TMR1-TMR4)
      • Table 18-3. TMR1-TMR4 Field Descriptions
    • 18.2.4 Timer Reference Registers (TRR1-TRR4)
      • Figure 18-6. Timer Reference Registers (TRR1-TRR4)
    • 18.2.5 Timer Capture Registers (TCR1-TCR4)
      • Figure 18-7. Timer Capture Registers (TCR1-TCR4)
    • 18.2.6 Timer Counters (TCN1-TCN4)
      • Figure 18-8. Timer Counter Registers (TCN1-TCN4)
    • 18.2.7 Timer Event Registers (TER1-TER4)
      • Figure 18-9. Timer Event Registers (TER1-TER4)
      • Table 18-4. TER Field Descriptions
• Chapter 19 SDMA Channels and IDMA Emulation
  • Figure 19-1. SDMA Data Paths
  • 19.1 SDMA Bus Arbitration and Bus Transfers
    • Figure 19-2. SDMA Bus Arbitration (Transaction Steal)
  • 19.2 SDMA Registers
    • 19.2.1 SDMA Status Register (SDSR)
      • Figure 19-3. SDMA Status Register (SDSR)
      • Table 19-1. SDSR Field Descriptions
    • 19.2.2 SDMA Mask Register (SDMR)
    • 19.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)
    • 19.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)
      • Figure 19-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)
      • Table 19-2. PDTEM and LDTEM Field Descriptions
  • 19.3 IDMA Emulation
  • 19.4 IDMA Features
  • 19.5 IDMA Transfers
    • 19.5.1 Memory-to-Memory Transfers
      • Table 19-3. IDMA Transfer Parameters (continued)
      • Figure 19-5. IDMA Transfer Buffer in the Dual-Port RAM
      • Figure 19-6. Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer (Size = 128 Bytes)
      • 19.5.1.1 External Request Mode
      • 19.5.1.2 Normal Mode
      • 19.5.1.3 Working with a PCI Bus
    • 19.5.2 Memory to/from Peripheral Transfers
      • 19.5.2.1 Dual-Address Transfers
        • 19.5.2.1.1 Peripheral to Memory
        • 19.5.2.1.2 Memory to Peripheral
      • 19.5.2.2 Single Address (Fly-By) Transfers
        • 19.5.2.2.1 Peripheral-to-Memory Fly-By Transfers
        • 19.5.2.2.2 Memory-to-Peripheral Fly-By Transfers
    • 19.5.3 Controlling 60x Bus Bandwidth
    • 19.5.4 PCI Burst Length and Latency Control
  • 19.6 IDMA Priorities
  • 19.7 IDMA Interface Signals
    • 19.7.1 DREQx and DACKx
      • 19.7.1.1 Level-Sensitive Mode
        • Figure 19-7. Timing Requirement for DREQ Negation when IMDA Read from a Peripheral
      • 19.7.1.2 Edge-Sensitive Mode
    • 19.7.2 DONEx
  • 19.8 IDMA Operation
    • 19.8.1 Auto Buffer and Buffer Chaining
      • Figure 19-8. IDMAx Channel’s BD Table
    • 19.8.2 IDMAx Parameter RAM
      • Table 19-4. IDMAx Parameter RAM (continued)
      • 19.8.2.1 DMA Channel Mode (DCM)
        • Figure 19-9. DCM Parameters
        • Table 19-5. DCM Field Descriptions (continued)
      • 19.8.2.2 Data Transfer Types as Programmed in DCM
        • Table 19-6. IDMA Channel Data Transfer Operation (continued)
      • 19.8.2.3 Programming DTS and STS
        • Table 19-7. Valid Memory-to-Memory STS/DTS Values
        • Table 19-8. Valid STS/DTS Values for Peripherals
    • 19.8.3 IDMA Performance
    • 19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
      • Figure 19-10. IDMA Event/Mask Registers (IDSR/IDMR)
      • Table 19-9. IDSR/IDMR Field Descriptions
    • 19.8.5 IDMA BDs
      • Figure 19-11. IDMA BD Structure
      • Table 19-10. IDMA BD Field Descriptions (continued)
  • 19.9 IDMA Commands
    • 19.9.1 start_idma Command
    • 19.9.2 stop_idma Command
  • 19.10 IDMA Bus Exceptions
    • Table 19-11. IDMA Bus Exceptions
    • 19.10.1 Externally Recognizing IDMA Operand Transfers
  • 19.11 Programming the Parallel I/O Registers
    • Table 19-12. Parallel I/O Register Programming-Port C
    • Table 19-13. Parallel I/O Register Programming-Port A
    • Table 19-14. Parallel I/O Register Programming-Port D
  • 19.12 IDMA Programming Examples
    • 19.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)-IDMA2
      • Table 19-15. Example: Peripheral-to-Memory Mode-IDMA2 (continued)
    • 19.12.2 Memory-to-Peripheral Fly-By Mode-IDMA3
      • Table 19-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)-IDMA3 (continued)
    • 19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)-IDMA1
      • Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)-IDMA1 (continued)
• Chapter 20 Serial Communications Controllers (SCCs)
  • Figure 20-1. SCC Block Diagram
  • 20.1 Features
    • 20.1.1 The General SCC Mode Registers (GSMR1-GSMR4)
      • Figure 20-2. GSMR_H-General SCC Mode Register (High Order)
      • Table 20-1. GSMR_H Field Descriptions (continued)
      • Figure 20-3. GSMR_L-General SCC Mode Register (Low Order)
      • Table 20-2. GSMR_L Field Descriptions (continued)
    • 20.1.2 Protocol-Specific Mode Register (PSMR)
    • 20.1.3 Data Synchronization Register (DSR)
      • Figure 20-4. Data Synchronization Register (DSR)
    • 20.1.4 Transmit-on-Demand Register (TODR)
      • Figure 20-5. Transmit-on-Demand Register (TODR)
      • Table 20-3. TODR Field Descriptions
  • 20.2 SCC Buffer Descriptors (BDs)
    • Figure 20-6. SCC Buffer Descriptors (BDs)
    • Figure 20-7. SCC BD and Buffer Memory Structure
  • 20.3 SCC Parameter RAM
    • Table 20-4. SCC Parameter RAM Map for All Protocols (continued)
    • 20.3.1 SCC Base Addresses
      • Table 20-5. Parameter RAM-SCC Base Addresses
    • 20.3.2 Function Code Registers (RFCR and TFCR)
      • Figure 20-8. Function Code Registers (RFCR and TFCR)
      • Table 20-6. RFCRx /TFCRx Field Descriptions
    • 20.3.3 Handling SCC Interrupts
      • Table 20-7. SCCx Event, Mask, and Status Registers
    • 20.3.4 Initializing the SCCs
    • 20.3.5 Controlling SCC Timing with RTS, CTS, and CD
      • 20.3.5.1 Synchronous Protocols
        • Figure 20-9. Output Delay from RTS Asserted for Synchronous Protocols
        • Figure 20-10. Output Delay from CTS Asserted for Synchronous Protocols
        • Figure 20-11. CTS Lost in Synchronous Protocols
        • Figure 20-12. Using CD to Control Synchronous Protocol Reception
      • 20.3.5.2 Asynchronous Protocols
    • 20.3.6 Digital Phase-Locked Loop (DPLL) Operation
      • Figure 20-13. DPLL Receiver Block Diagram
      • Figure 20-14. DPLL Transmitter Block Diagram
      • Table 20-8. Preamble Requirements (continued)
      • 20.3.6.1 Encoding Data with a DPLL
        • Figure 20-15. DPLL Encoding Examples
        • Table 20-9. DPLL Codings
    • 20.3.7 Reconfiguring the SCCs
      • 20.3.7.1 General Reconfiguration Sequence for an SCC Transmitter
      • 20.3.7.2 Reset Sequence for an SCC Transmitter
      • 20.3.7.3 General Reconfiguration Sequence for an SCC Receiver
      • 20.3.7.4 Reset Sequence for an SCC Receiver
      • 20.3.7.5 Switching Protocols
    • 20.3.8 Saving Power
• Chapter 21 SCC UART Mode
  • Figure 21-1. UART Character Format
  • 21.1 Features
  • 21.2 Normal Asynchronous Mode
  • 21.3 Synchronous Mode
  • 21.4 SCC UART Parameter RAM
    • Table 21-1. UART-Specific SCC Parameter RAM Memory Map (continued)
  • 21.5 Data-Handling Methods: Character- or Message-Based
  • 21.6 Error and Status Reporting
  • 21.7 SCC UART Commands
    • Table 21-2. Transmit Commands
    • Table 21-3. Receive Commands
  • 21.8 Multidrop Systems and Address Recognition
    • Figure 21-2. Two UART Multidrop Configurations
  • 21.9 Receiving Control Characters
    • Figure 21-3. Control Character Table
    • Table 21-4. Control Character Table, RCCM, and RCCR Descriptions
  • 21.10 Hunt Mode (Receiver)
  • 21.11 Inserting Control Characters into the Transmit Data Stream
    • Figure 21-4. Transmit Out-of-Sequence Register (TOSEQ)
    • Table 21-5. TOSEQ Field Descriptions (continued)
  • 21.12 Sending a Break (Transmitter)
  • 21.13 Sending a Preamble (Transmitter)
  • 21.14 Fractional Stop Bits (Transmitter)
    • Figure 21-5. Asynchronous UART Transmitter
    • Table 21-6. DSR Fields Descriptions
  • 21.15 Handling Errors in the SCC UART Controller
    • Table 21-7. Transmission Errors
    • Table 21-8. Reception Errors
  • 21.16 UART Mode Register (PSMR)
    • Figure 21-6. Protocol-Specific Mode Register for UART (PSMR)
    • Table 21-9. PSMR UART Field Descriptions (continued)
  • 21.17 SCC UART Receive Buffer Descriptor (RxBD)
    • Figure 21-7. SCC UART Receiving using RxBDs
    • Figure 21-8. SCC UART Receive Buffer Descriptor (RxBD)
    • Table 21-10. SCC UART RxBD Status and Control Field Descriptions (continued)
  • 21.18 SCC UART Transmit Buffer Descriptor (TxBD)
    • Figure 21-9. SCC UART Transmit Buffer Descriptor (TxBD)
    • Table 21-11. SCC UART TxBD Status and Control Field Descriptions (continued)
  • 21.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
    • Figure 21-10. SCC UART Interrupt Event Example
    • Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)
    • Table 21-12. SCCE/SCCM Field Descriptions for UART Mode
  • 21.20 SCC UART Status Register (SCCS)
    • Figure 21-12. SCC Status Register for UART Mode (SCCS)
    • Table 21-13. UART SCCS Field Descriptions
  • 21.21 SCC UART Programming Example
  • 21.22 S-Records Loader Application
    • Table 21-14. UART Control Characters for S-Records Example (continued)
• Chapter 22 SCC HDLC Mode
  • 22.1 SCC HDLC Features
  • 22.2 SCC HDLC Channel Frame Transmission
    • Figure 22-1. HDLC Framing Structure
  • 22.3 SCC HDLC Channel Frame Reception
  • 22.4 SCC HDLC Parameter RAM
    • Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map (continued)
    • Figure 22-2. HDLC Address Recognition
  • 22.5 Programming the SCC in HDLC Mode
  • 22.6 SCC HDLC Commands
    • Table 22-2. Transmit Commands
    • Table 22-3. Receive Commands
  • 22.7 Handling Errors in the SCC HDLC Controller
    • Table 22-4. Transmit Errors
    • Table 22-5. Receive Errors
  • 22.8 HDLC Mode Register (PSMR)
    • Figure 22-3. HDLC Mode Register (PSMR)
    • Table 22-6. PSMR HDLC Field Descriptions (continued)
  • 22.9 SCC HDLC Receive Buffer Descriptor (RxBD)
    • Figure 22-4. SCC HDLC Receive Buffer Descriptor (RxBD)
    • Table 22-7. SCC HDLC RxBD Status and Control Field Descriptions (continued)
    • Figure 22-5. SCC HDLC Receiving Using RxBDs
  • 22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
    • Figure 22-6. SCC HDLC Transmit Buffer Descriptor (TxBD)
    • Table 22-8. SCC HDLC TxBD Status and Control Field Descriptions
  • 22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
    • Figure 22-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
    • Table 22-9. SCCE/SCCM Field Descriptions (continued)
    • Figure 22-8. SCC HDLC Interrupt Event Example
  • 22.12 SCC HDLC Status Register (SCCS)
    • Figure 22-9. CC HDLC Status Register (SCCS)
    • Table 22-10. HDLC SCCS Field Descriptions
  • 22.13 SCC HDLC Programming Examples
  • 22.14 SCC HDLC Programming Example #1
    • 22.14.1 SCC HDLC Programming Example #2
  • 22.15 HDLC Bus Mode with Collision Detection
    • Figure 22-10. Typical HDLC Bus Multimaster Configuration
    • Figure 22-11. Typical HDLC Bus Single-Master Configuration
    • 22.15.1 HDLC Bus Features
    • 22.15.2 Accessing the HDLC Bus
      • Figure 22-12. Detecting an HDLC Bus Collision
    • 22.15.3 Increasing Performance
      • Figure 22-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance
    • 22.15.4 Delayed RTS Mode
      • Figure 22-14. HDLC Bus Transmission Line Configuration
      • Figure 22-15. Delayed RTS Mode
    • 22.15.5 Using the Time-Slot Assigner (TSA)
      • Figure 22-16. HDLC Bus TDM Transmission Line Configuration
    • 22.15.6 HDLC Bus Protocol Programming
      • 22.15.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
      • 22.15.6.2 HDLC Bus Controller Programming Example
• Chapter 23 SCC BISYNC Mode
  • Figure 23-1. Classes of BISYNC Frames
  • 23.1 Features
  • 23.2 SCC BISYNC Channel Frame Transmission
  • 23.3 SCC BISYNC Channel Frame Reception
  • 23.4 SCC BISYNC Parameter RAM
    • Table 23-1. SCC BISYNC Parameter RAM Memory Map
  • 23.5 SCC BISYNC Commands
    • Table 23-2. Transmit Commands
    • Table 23-3. Receive Commands
  • 23.6 SCC BISYNC Control Character Recognition
    • Figure 23-2. Control Character Table and RCCM
    • Table 23-4. Control Character Table and RCCM Field Descriptions
  • 23.7 BISYNC SYNC Register (BSYNC)
    • Figure 23-3. BISYNC SYNC (BSYNC)
    • Table 23-5. BSYNC Field Descriptions
  • 23.8 SCC BISYNC DLE Register (BDLE)
    • Figure 23-4. BISYNC DLE (BDLE)
    • Table 23-6. BDLE Field Descriptions
  • 23.9 Sending and Receiving the Synchronization Sequence
    • Table 23-7. Receiver SYNC Pattern Lengths of the DSR
  • 23.10 Handling Errors in the SCC BISYNC
    • Table 23-8. Transmit Errors
    • Table 23-9. Receive Errors
  • 23.11 BISYNC Mode Register (PSMR)
    • Figure 23-5. Protocol-Specific Mode Register for BISYNC (PSMR)
    • Table 23-10. PSMR Field Descriptions (continued)
  • 23.12 SCC BISYNC Receive BD (RxBD)
    • Figure 23-6. SCC BISYNC RxBD
    • Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions (continued)
  • 23.13 SCC BISYNC Transmit BD (TxBD)
    • Figure 23-7. SCC BISYNC Transmit BD (TxBD)
    • Table 23-12. SCC BISYNC TxBD Status and Control Field Descriptions (continued)
  • 23.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    • Figure 23-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    • Table 23-13. SCCE/SCCM Field Descriptions
  • 23.15 SCC Status Registers (SCCS)
    • Figure 23-9. SCC Status Registers (SCCS)
    • Table 23-14. SCCS Field Descriptions
  • 23.16 Programming the SCC BISYNC Controller
    • Table 23-15. Control Characters
  • 23.17 SCC BISYNC Programming Example
• Chapter 24 SCC Transparent Mode
  • 24.1 Features
  • 24.2 SCC Transparent Channel Frame Transmission Process
  • 24.3 SCC Transparent Channel Frame Reception Process
  • 24.4 Achieving Synchronization in Transparent Mode
    • 24.4.1 Synchronization in NMSI Mode
      • 24.4.1.1 In-Line Synchronization Pattern
        • Table 24-1. Receiver SYNC Pattern Lengths of the DSR
      • 24.4.1.2 External Synchronization Signals
        • 24.4.1.2.1 External Synchronization Example
          • Figure 24-1. Sending Transparent Frames between PowerQUICC IIs
      • 24.4.1.3 Transparent Mode without Explicit Synchronization
    • 24.4.2 Synchronization and the TSA
      • 24.4.2.1 Inline Synchronization Pattern
      • 24.4.2.2 Inherent Synchronization
    • 24.4.3 End of Frame Detection
  • 24.5 CRC Calculation in Transparent Mode
  • 24.6 SCC Transparent Parameter RAM
    • Table 24-2. SCC Transparent Parameter RAM Memory Map
  • 24.7 SCC Transparent Commands
    • Table 24-3. Transmit Commands (continued)
    • Table 24-4. Receive Commands
  • 24.8 Handling Errors in the Transparent Controller
    • Table 24-5. Transmit Errors
    • Table 24-6. Receive Errors
  • 24.9 Transparent Mode and the PSMR
  • 24.10 SCC Transparent Receive Buffer Descriptor (RxBD)
    • Figure 24-2. SCC Transparent Receive Buffer Descriptor (RxBD)
    • Table 24-7. SCC Transparent RxBD Status and Control Field Descriptions
  • 24.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
    • Figure 24-3. SCC Transparent Transmit Buffer Descriptor (TxBD)
    • Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions (continued) (continued)
  • 24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
    • Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
    • Table 24-9. SCCE/SCCM Field Descriptions (continued)
  • 24.13 SCC Status Register in Transparent Mode (SCCS)
    • Figure 24-5. SCC Status Register in Transparent Mode (SCCS)
    • Table 24-10. SCCS Field Descriptions
  • 24.14 SCC2 Transparent Programming Example
• Chapter 25 SCC Ethernet Mode
  • Figure 25-1. Ethernet Frame Structure
  • 25.1 Ethernet on the PowerQUICC II
    • Figure 25-2. Ethernet Block Diagram
  • 25.2 Features
  • 25.3 Connecting the PowerQUICC II to Ethernet
    • Figure 25-3. Connecting the PowerQUICC II to Ethernet
  • 25.4 SCC Ethernet Channel Frame Transmission
  • 25.5 SCC Ethernet Channel Frame Reception
  • 25.6 The Content-Addressable Memory (CAM) Interface
  • 25.7 SCC Ethernet Parameter RAM
    • Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued)
  • 25.8 Programming the Ethernet Controller
  • 25.9 SCC Ethernet Commands
    • Table 25-2. Transmit Commands
    • Table 25-3. Receive Commands
  • 25.10 SCC Ethernet Address Recognition
    • Figure 25-4. Ethernet Address Recognition Flowchart
  • 25.11 Hash Table Algorithm
  • 25.12 Interpacket Gap Time
  • 25.13 Handling Collisions
  • 25.14 Internal and External Loopback
  • 25.15 Full-Duplex Ethernet Support
  • 25.16 Handling Errors in the Ethernet Controller
    • Table 25-4. Transmission Errors (continued)
    • Table 25-5. Reception Errors
  • 25.17 Ethernet Mode Register (PSMR)
    • Figure 25-5. Ethernet Mode Register (PSMR)
    • Table 25-6. PSMR Field Descriptions
  • 25.18 SCC Ethernet Receive BD
    • Figure 25-6. SCC Ethernet RxBD
    • Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions (continued)
    • Figure 25-7. Ethernet Receiving using RxBDs
  • 25.19 SCC Ethernet Transmit Buffer Descriptor
    • Figure 25-8. SCC Ethernet TxBD
    • Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions (continued)
  • 25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
    • Figure 25-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
    • Table 25-9. SCCE/SCCM Field Descriptions (continued)
    • Figure 25-10. Ethernet Interrupt Events Example
  • 25.21 SCC Ethernet Programming Example
• Chapter 26 SCC AppleTalk Mode
  • 26.1 Operating the LocalTalk Bus
    • Figure 26-1. LocalTalk Frame Format
  • 26.2 Features
  • 26.3 Connecting to AppleTalk
    • Figure 26-2. Connecting the PowerQUICC II to LocalTalk
  • 26.4 Programming the SCC in AppleTalk Mode
    • 26.4.1 Programming the GSMR
    • 26.4.2 Programming the PSMR
    • 26.4.3 Programming the TODR
    • 26.4.4 SCC AppleTalk Programming Example
• Chapter 27 Serial Management Controllers (SMCs)
  • Figure 27-1. SMC Block Diagram
  • 27.1 Features
  • 27.2 Common SMC Settings and Configurations
    • 27.2.1 SMC Mode Registers (SMCMR1/SMCMR2)
      • Figure 27-2. SMC Mode Registers (SMCMR1/SMCMR2)
      • Table 27-1. SMCMR1/SMCMR2 Field Descriptions (continued)
    • 27.2.2 SMC Buffer Descriptor Operation
      • Figure 27-3. SMC Memory Structure
    • 27.2.3 SMC Parameter RAM
      • Table 27-2. SMC UART and Transparent Parameter RAM Memory Map (continued)
      • 27.2.3.1 SMC Function Code Registers (RFCR/TFCR)
        • Figure 27-4. SMC Function Code Registers (RFCR/TFCR)
        • Table 27-3. RFCR/TFCR Field Descriptions
    • 27.2.4 Disabling SMCs On-the-Fly
      • 27.2.4.1 SMC Transmitter Full Sequence
      • 27.2.4.2 SMC Transmitter Shortcut Sequence
      • 27.2.4.3 SMC Receiver Full Sequence
      • 27.2.4.4 SMC Receiver Shortcut Sequence
      • 27.2.4.5 Switching Protocols
    • 27.2.5 Saving Power
    • 27.2.6 Handling Interrupts in the SMC
  • 27.3 SMC in UART Mode
    • Figure 27-5. SMC UART Frame Format
    • 27.3.1 Features
    • 27.3.2 SMC UART Channel Transmission Process
    • 27.3.3 SMC UART Channel Reception Process
    • 27.3.4 Programming the SMC UART Controller
    • 27.3.5 SMC UART Transmit and Receive Commands
      • Table 27-4. Transmit Commands
      • Table 27-5. Receive Commands
    • 27.3.6 Sending a Break
    • 27.3.7 Sending a Preamble
    • 27.3.8 Handling Errors in the SMC UART Controller
      • Table 27-6. SMC UART Errors
    • 27.3.9 SMC UART RxBD
      • Figure 27-6. SMC UART RxBD
      • Table 27-7. SMC UART RxBD Field Descriptions (continued)
      • Figure 27-7. RxBD Example
    • 27.3.10 SMC UART TxBD
      • Figure 27-8. SMC UART TxBD
      • Table 27-8. SMC UART TxBD Field Descriptions
    • 27.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
      • Figure 27-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)
      • Table 27-9. SMCE/SMCM Field Descriptions
      • Figure 27-10. SMC UART Interrupts Example
    • 27.3.12 SMC UART Controller Programming Example
  • 27.4 SMC in Transparent Mode
    • 27.4.1 Features
    • 27.4.2 SMC Transparent Channel Transmission Process
    • 27.4.3 SMC Transparent Channel Reception Process
    • 27.4.4 Using SMSYN for Synchronization
      • Figure 27-11. Synchronization with SMSYNx
    • 27.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
      • Figure 27-12. Synchronization with the TSA
    • 27.4.6 SMC Transparent Commands
      • Table 27-10. SMC Transparent Transmit Commands
      • Table 27-11. SMC Transparent Receive Commands
    • 27.4.7 Handling Errors in the SMC Transparent Controller
      • Table 27-12. SMC Transparent Error Conditions
    • 27.4.8 SMC Transparent RxBD
      • Figure 27-13. SMC Transparent RxBD
      • Table 27-13. SMC Transparent RxBD Field Descriptions (continued)
    • 27.4.9 SMC Transparent TxBD
      • Table 27-14. SMC Transparent TxBD
      • Table 27-15. SMC Transparent TxBD Field Descriptions
    • 27.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
      • Figure 27-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
      • Table 27-16. SMCE/SMCM Field Descriptions
    • 27.4.11 SMC Transparent NMSI Programming Example
  • 27.5 The SMC in GCI Mode
    • 27.5.1 SMC GCI Parameter RAM
      • Table 27-17. SMC GCI Parameter RAM Memory Map
    • 27.5.2 Handling the GCI Monitor Channel
      • 27.5.2.1 SMC GCI Monitor Channel Transmission Process
      • 27.5.2.2 SMC GCI Monitor Channel Reception Process
    • 27.5.3 Handling the GCI C/I Channel
      • 27.5.3.1 SMC GCI C/I Channel Transmission Process
      • 27.5.3.2 SMC GCI C/I Channel Reception Process
    • 27.5.4 SMC GCI Commands
      • Table 27-18. SMC GCI Commands
    • 27.5.5 SMC GCI Monitor Channel RxBD
      • Figure 27-15. SMC Monitor Channel RxBD
      • Table 27-19. SMC Monitor Channel RxBD Field Descriptions
    • 27.5.6 SMC GCI Monitor Channel TxBD
      • Figure 27-16. SMC Monitor Channel TxBD
      • Table 27-20. SMC Monitor Channel TxBD Field Descriptions
    • 27.5.7 SMC GCI C/I Channel RxBD
      • Figure 27-17. SMC C/I Channel RxBD
      • Table 27-21. SMC C/I Channel RxBD Field Descriptions
    • 27.5.8 SMC GCI C/I Channel TxBD
      • Figure 27-18. SMC C/I Channel TxBD
      • Table 27-22. SMC C/I Channel TxBD Field Descriptions
    • 27.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
      • Figure 27-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM)
      • Table 27-23. SMCE/SMCM Field Descriptions
• Chapter 28 Multi-Channel Controllers (MCCs)
  • 28.1 MCC Operation Overview
    • 28.1.1 MCC Data Structure Organization
      • Figure 28-1. BD Structure for One MCC
  • 28.2 Global MCC Parameters
    • Table 28-1. Global MCC Parameters (continued)
  • 28.3 Channel-Specific Parameters
    • 28.3.1 Channel-Specific HDLC Parameters
      • Table 28-2. Channel-Specific Parameters for HDLC (continued)
      • 28.3.1.1 Internal Transmitter State (TSTATE)-HDLC Mode
        • Figure 28-2. TSTATE High Byte
        • Table 28-3. TSTATE High-Byte Field Descriptions
      • 28.3.1.2 Interrupt Mask (INTMSK)-HDLC Mode
        • Figure 28-3. INTMSK Mask Bits
      • 28.3.1.3 Channel Mode Register (CHAMR)-HDLC Mode
        • Figure 28-4. Channel Mode Register (CHAMR)
        • Table 28-4. CHAMR Field Descriptions (continued)
      • 28.3.1.4 Internal Receiver State (RSTATE)-HDLC Mode
        • Figure 28-5. Rx Internal State (RSTATE) High Byte
        • Table 28-5. RSTATE High-Byte Field Descriptions (continued)
    • 28.3.2 Channel-Specific Transparent Parameters
      • Table 28-6. Channel-Specific Parameters for Transparent Operation (continued)
      • 28.3.2.1 Internal Transmitter State (TSTATE)-Transparent Mode
      • 28.3.2.2 Interrupt Mask (INTMSK)-Transparent Mode
      • 28.3.2.3 Channel Mode Register (CHAMR)-Transparent Mode
        • Figure 28-6. Channel Mode Register (CHAMR)-Transparent Mode
        • Table 28-7. CHAMR Field Descriptions-Transparent Mode (continued)
      • 28.3.2.4 Internal Receiver State (RSTATE)-Transparent Mode
    • 28.3.3 MCC Parameters for AAL1 CES Usage
      • 28.3.3.1 Channel-Specific Parameters-AAL1 CES
        • Table 28-8. CES-Specific Global MCC Parameters
        • 28.3.3.1.1 Interrupt Circular Table Entry and Interrupt Mask (INTMSK)-AAL1 CES
          • Figure 28-7. INTMSK Mask Bits
      • 28.3.3.2 Channel Mode Register (CHAMR)-AAL1 CES
        • Figure 28-8. Channel Mode Register (CHAMR)-CES Mode
        • Table 28-9. CHAMR Field Descriptions-CES Mode (continued)
    • 28.3.4 Channel-Specific SS7 Parameters
      • Table 28-10. Channel-Specific Parameters for SS7 (continued)
      • 28.3.4.1 Extended Channel Mode Register (ECHAMR)-SS7 Mode
        • Figure 28-9. Extended Channel Mode Register (ECHAMR)
        • Table 28-11. ECHAMR Fields Description (continued)
      • 28.3.4.2 Signal Unit Error Monitor (SUERM)-SS7 Mode
        • 28.3.4.2.1 SUERM in Japanese SS7
          • Table 28-12. Parameter Values for SUERM in Japanese SS7
      • 28.3.4.3 SS7 Configuration Register-SS7 Mode
        • Figure 28-10. SS7 Configuration Register (SS7_OPT)
        • Table 28-13. SS7 Configuration Register Fields Description
        • 28.3.4.3.1 AERM Implementation
        • 28.3.4.3.2 AERM in Japanese SS7
        • 28.3.4.3.3 Disabling SUERM
      • 28.3.4.4 SU Filtering-SS7 Mode
        • 28.3.4.4.1 Comparison Mask
          • Figure 28-11. Mask1 Format
          • Figure 28-12. Mask2 Format
        • 28.3.4.4.2 Comparison State Machine
        • 28.3.4.4.3 Filtering Limitations
        • 28.3.4.4.4 Resetting the SU Filtering Mechanism
      • 28.3.4.5 Octet Counting Mode-SS7 Mode
  • 28.4 Channel Extra Parameters
    • Table 28-14. Channel Extra Parameters
  • 28.5 Superchannels
    • 28.5.1 Superchannel Table
      • Figure 28-13. Super Channel Table Entry
    • 28.5.2 Superchannels and Receiving
    • 28.5.3 Transparent Slot Synchronization
    • 28.5.4 Superchannelling Programming Examples
      • Figure 28-14. Transmitter Super Channel Example
      • Figure 28-15. Receiver Super Channel with Slot Synchronization Example
      • Figure 28-16. Receiver Super Channel without Slot Synchronization Example
  • 28.6 MCC Configuration Registers (MCCFx)
    • Figure 28-17. SI MCC Configuration Register (MCCF)
    • Table 28-15. MCCF Field Descriptions
    • Table 28-16. Group Channel Assignments
  • 28.7 MCC Commands
    • Table 28-17. MCC Commands
  • 28.8 MCC Exceptions
    • Figure 28-18. Interrupt Circular Table
    • 28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)
      • Figure 28-19. MCC Event Register (MCCE)/Mask Register (MCCM)
      • Table 28-18. MCCE/MCCM Register Field Descriptions (continued)
      • 28.8.1.1 Interrupt Circular Table Entry
        • Figure 28-20. Interrupt Circular Table Entry
        • Table 28-19. Interrupt Circular Table Entry Field Descriptions (continued)
      • 28.8.1.2 Global Transmitter Underrun (GUN)
        • 28.8.1.2.1 TDM Clock
        • 28.8.1.2.2 Synchronization Pulse
        • 28.8.1.2.3 SIRAM Programming
        • 28.8.1.2.4 MCC Initialization
        • 28.8.1.2.5 CPM Bandwidth
        • 28.8.1.2.6 CPM Priority
        • 28.8.1.2.7 Bus Latency
      • 28.8.1.3 Recovery from GUN Errors
        • Table 28-20. GUN Error Recovery-.29mm (HiP3) Rev A.1 and B.2 Silicon
        • Table 28-21. GUN Error Recovery-.29mm (HiP3) Rev B.3 and Subsequent Silicon
      • 28.8.1.4 Global Overrun (GOV)
  • 28.9 MCC Buffer Descriptors
    • 28.9.1 Receive Buffer Descriptor (RxBD)
      • Figure 28-21. MCC Receive Buffer Descriptor (RxBD)
      • Table 28-22. RxBD Field Descriptions (continued)
    • 28.9.2 Transmit Buffer Descriptor (TxBD)
      • Figure 28-22. MCC Transmit Buffer Descriptor (TxBD)
      • Table 28-23. TxBD Field Descriptions (continued)
  • 28.10 MCC Initialization and Start/Stop Sequence
    • 28.10.1 Stopping and Restarting a Single-Channel
    • 28.10.2 Stopping and Restarting a Superchannel
  • 28.11 MCC Latency and Performance
• Chapter 29 Fast Communications Controllers (FCCs)
  • 29.1 Overview
    • Figure 29-1. FCC Block Diagram
    • Table 29-1. Internal Clocks to CPM Clock Frequency Ratio
  • 29.2 General FCC Mode Registers (GFMRx)
    • Figure 29-2. General FCC Mode Register (GFMR)
    • Table 29-2. GFMR Register Field Descriptions (continued)
  • 29.3 FCC Protocol-Specific Mode Registers (FPSMRx)
  • 29.4 FCC Data Synchronization Registers (FDSRx)
    • Figure 29-3. FCC Data Synchronization Register (FDSR)
  • 29.5 FCC Transmit-on-Demand Registers (FTODRx)
    • Figure 29-4. FCC Transmit-on-Demand Register (FTODR)
    • Table 29-3. FTODR Field Descriptions
  • 29.6 FCC Buffer Descriptors
    • Figure 29-5. FCC Memory Structure
    • Figure 29-6. Buffer Descriptor Format
  • 29.7 FCC Parameter RAM
    • Table 29-4. FCC Parameter RAM Common to All Protocols except ATM (continued)
    • 29.7.1 FCC Function Code Registers (FCRx)
      • Figure 29-7. Function Code Register (FCRx)
      • Table 29-5. FCRx Field Descriptions
  • 29.8 Interrupts from the FCCs
    • 29.8.1 FCC Event Registers (FCCEx)
    • 29.8.2 FCC Mask Registers (FCCMx)
    • 29.8.3 FCC Status Registers (FCCSx)
  • 29.9 FCC Initialization
  • 29.10 FCC Interrupt Handling
    • 29.10.1 FCC Transmit Errors
      • 29.10.1.1 Re-Initialization Procedure
      • 29.10.1.2 Recovery Sequence
      • 29.10.1.3 Adjusting Transmitter BD Handling
  • 29.11 FCC Timing Control
    • Figure 29-8. Output Delay from RTS Asserted
    • Figure 29-9. Output Delay from CTS Asserted
    • Figure 29-10. CTS Lost
    • Figure 29-11. Using CD to Control Reception
  • 29.12 Disabling the FCCs On-the-Fly
    • 29.12.1 FCC Transmitter Full Sequence
    • 29.12.2 FCC Transmitter Shortcut Sequence
    • 29.12.3 FCC Receiver Full Sequence
    • 29.12.4 FCC Receiver Shortcut Sequence
    • 29.12.5 Switching Protocols
  • 29.13 Saving Power
• Chapter 30 ATM Controller and AAL0, AAL1, and AAL5
  • 30.1 Features
  • 30.2 ATM Controller Overview
    • 30.2.1 Transmitter Overview
      • 30.2.1.1 AAL5 Transmitter Overview
      • 30.2.1.2 AAL1 Transmitter Overview
        • 30.2.1.2.1 AAL1 CES Transmitter Overview
      • 30.2.1.3 AAL0 Transmitter Overview
      • 30.2.1.4 AAL2 Transmitter Overview
      • 30.2.1.5 Transmit External Rate and Internal Rate Modes
    • 30.2.2 Receiver Overview
      • 30.2.2.1 AAL5 Receiver Overview
      • 30.2.2.2 AAL1 Receiver Overview
        • 30.2.2.2.1 AAL1 CES Receiver Overview
      • 30.2.2.3 AAL0 Receiver Overview
      • 30.2.2.4 AAL2 Receiver Overview
    • 30.2.3 Performance Monitoring
    • 30.2.4 ABR Flow Control
  • 30.3 ATM Pace Control (APC) Unit
    • 30.3.1 APC Modes and ATM Service Types
      • Table 30-1. ATM Service Types
    • 30.3.2 APC Unit Scheduling Mechanism
      • Figure 30-1. APC Scheduling Table Mechanism
    • 30.3.3 Determining the Scheduling Table Size
      • 30.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table
      • 30.3.3.2 Determining the Number of Slots in a Scheduling Table
    • 30.3.4 Determining the Time-Slot Scheduling Rate of a Channel
    • 30.3.5 ATM Traffic Type
      • 30.3.5.1 Peak Cell Rate Traffic Type
      • 30.3.5.2 Determining the PCR Traffic Type Parameters
      • 30.3.5.3 Peak and Sustain Traffic Type (VBR)
        • Figure 30-2. VBR Pacing Using the GCRA (Leaky Bucket Algorithm)
        • 30.3.5.3.1 Example for Using VBR Traffic Parameters
        • 30.3.5.3.2 Handling the Cell Loss Priority (CLP)-VBR Type 1 and 2
      • 30.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)
    • 30.3.6 Determining the Priority of an ATM Channel
  • 30.4 VCI/VPI Address Lookup Mechanism
    • 30.4.1 External CAM Lookup
      • Figure 30-3. External CAM Data Input Fields
      • Figure 30-4. External CAM Output Fields
      • Table 30-2. External CAM Input and Output Field Descriptions
    • 30.4.2 Address Compression
      • Figure 30-5. Address Compression Mechanism
      • Table 30-3. Field Descriptions for Address Compression
      • 30.4.2.1 VP-Level Address Compression Table (VPLT)
        • Figure 30-6. General VCOFFSET Formula for Contiguous VCLTs
        • Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs
        • Table 30-5. VP-Level Table Entry Address Calculation Example
        • Figure 30-7. VP Pointer Address Compression
      • 30.4.2.2 VC-Level Address Compression Tables (VCLTs)
        • Table 30-6. VC-Level Table Entry Address Calculation Example
        • Figure 30-8. VC Pointer Address Compression
    • 30.4.3 Misinserted Cells
    • 30.4.4 Receive Raw Cell Queue
      • Figure 30-9. ATM Address Recognition Flowchart
  • 30.5 Available Bit Rate (ABR) Flow Control
    • 30.5.1 The ABR Model
      • Figure 30-10. PowerQUICC II’s ABR Basic Model
      • 30.5.1.1 ABR Flow Control Source End-System Behavior
      • 30.5.1.2 ABR Flow Control Destination End-System Behavior
      • 30.5.1.3 ABR Flowcharts
        • Figure 30-11. ABR Transmit Flow
        • Figure 30-12. ABR Transmit Flow (Continued)
        • Figure 30-13. ABR Transmit Flow (Continued)
        • Figure 30-14. ABR Receive Flow
    • 30.5.2 RM Cell Structure
      • Table 30-7. Fields and their Positions in RM Cells
      • 30.5.2.1 RM Cell Rate Representation
        • Figure 30-15. Rate Format for RM Cells
        • Figure 30-16. Rate Formula for RM Cells
    • 30.5.3 ABR Flow Control Setup
  • 30.6 OAM Support
    • 30.6.1 ATM-Layer OAM Definitions
      • Table 30-8. Pre-Assigned Header Values at the UNI
      • Table 30-9. Pre-Assigned Header Values at the NNI
    • 30.6.2 Virtual Path (F4) Flow Mechanism
    • 30.6.3 Virtual Channel (F5) Flow Mechanism
    • 30.6.4 Receiving OAM F4 or F5 Cells
    • 30.6.5 Transmitting OAM F4 or F5 Cells
    • 30.6.6 Performance Monitoring
      • Figure 30-17. Performance Monitoring Cell Structure (FMCs and BRCs)
      • Table 30-10. Performance Monitoring Cell Fields
      • 30.6.6.1 Running a Performance Block Test
      • 30.6.6.2 PM Block Monitoring
      • 30.6.6.3 PM Block Generation
        • Figure 30-18. FMC, BRC Insertion
      • 30.6.6.4 BRC Performance Calculations
  • 30.7 User-Defined Cells (UDC)
    • Figure 30-19. Format of User-Defined Cells
    • 30.7.1 UDC Extended Address Mode (UEAD)
      • Figure 30-20. External CAM Address in UDC Extended Address Mode
  • 30.8 ATM Layer Statistics
  • 30.9 ATM-to-TDM Interworking
    • 30.9.1 Automatic Data Forwarding
      • Figure 30-21. ATM-to-TDM Interworking
    • 30.9.2 Using Interrupts in Automatic Data Forwarding
    • 30.9.3 Timing Issues
    • 30.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
    • 30.9.5 Mapping TDM Time Slots to VCs
    • 30.9.6 CAS Support
    • 30.9.7 Trunk Condition
    • 30.9.8 ATM-to-ATM Data Forwarding
  • 30.10 ATM Memory Structure
    • 30.10.1 Parameter RAM
      • Table 30-11. ATM Parameter RAM Map (continued)
      • 30.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)
        • Table 30-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header
      • 30.10.1.2 VCI Filtering (VCIF)
        • Figure 30-22. VCI Filtering Enable Bits
        • Table 30-13. VCI Filtering Enable Field Descriptions
      • 30.10.1.3 Global Mode Entry (GMODE)
        • Figure 30-23. Global Mode Entry (GMODE)
        • Table 30-14. GMODE Field Descriptions (continued)
    • 30.10.2 Connection Tables (RCT, TCT, and TCTE)
      • Table 30-15. Receive and Transmit Connection Table Sizes
      • 30.10.2.1 ATM Channel Code
        • Figure 30-24. Example of a 1024-Entry Receive Connection Table
      • 30.10.2.2 Receive Connection Table (RCT)
        • Figure 30-25. Receive Connection Table (RCT) Entry
        • Table 30-16. RCT Field Descriptions (continued)
        • 30.10.2.2.1 AAL5 Protocol-Specific RCT
          • Figure 30-26. AAL5 Protocol-Specific RCT
          • Table 30-17. RCT Settings (AAL5 Protocol-Specific)
        • 30.10.2.2.2 AAL5-ABR Protocol-Specific RCT
          • Figure 30-27. AAL5-ABR Protocol-Specific RCT
          • Table 30-18. ABR Protocol-Specific RCT Field Descriptions
        • 30.10.2.2.3 AAL1 Protocol-Specific RCT
          • Figure 30-28. AAL1 Protocol-Specific RCT
          • Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions (continued)
        • 30.10.2.2.4 AAL0 Protocol-Specific RCT
          • Figure 30-29. AAL0 Protocol-Specific RCT
          • Table 30-20. AAL0-Specific RCT Field Descriptions (continued)
        • 30.10.2.2.5 AAL1 CES Protocol-Specific RCT
        • 30.10.2.2.6 AAL2 Protocol-Specific RCT
      • 30.10.2.3 Transmit Connection Table (TCT)
        • Figure 30-30. Transmit Connection Table (TCT) Entry
        • Table 30-21. TCT Field Descriptions (continued)
        • 30.10.2.3.1 AAL5 Protocol-Specific TCT
          • Figure 30-31. AAL5 Protocol-Specific TCT
          • Table 30-22. AAL5-Specific TCT Field Descriptions
        • 30.10.2.3.2 AAL1 Protocol-Specific TCT
          • Figure 30-32. AAL1 Protocol-Specific TCT
          • Table 30-23. AAL1 Protocol-Specific TCT Field Descriptions
        • 30.10.2.3.3 AAL0 Protocol-Specific TCT
          • Figure 30-33. AAL0 Protocol-Specific TCT
          • Table 30-24. AAL0-Specific TCT Field Descriptions
        • 30.10.2.3.4 AAL1 CES Protocol-Specific TCT
        • 30.10.2.3.5 AAL2 Protocol-Specific TCT
        • 30.10.2.3.6 VBR Protocol-Specific TCTE
          • Figure 30-34. Transmit Connection Table Extension (TCTE)-VBR Protocol-Specific
          • Table 30-25. VBR-Specific TCTE Field Descriptions
        • 30.10.2.3.7 UBR+ Protocol-Specific TCTE
          • Figure 30-35. UBR+ Protocol-Specific TCTE
          • Table 30-26. UBR+ Protocol-Specific TCTE Field Descriptions
        • 30.10.2.3.8 ABR Protocol-Specific TCTE
          • Figure 30-36. ABR Protocol-Specific TCTE
          • Table 30-27. ABR-Specific TCTE Field Descriptions (continued)
    • 30.10.3 OAM Performance Monitoring Tables
      • Figure 30-37. OAM Performance Monitoring Table
      • Table 30-28. OAM-Performance Monitoring Table Field Descriptions
    • 30.10.4 APC Data Structure
      • Figure 30-38. ATM Pace Control Data Structure
      • 30.10.4.1 APC Parameter Tables
        • Table 30-29. APC Parameter Table (continued)
      • 30.10.4.2 APC Priority Table
        • Table 30-30. APC Priority Table Entry
      • 30.10.4.3 APC Scheduling Tables
        • Figure 30-39. The APC Scheduling Table Structure
        • Figure 30-40. Control Slot
        • Table 30-31. Control Slot Field Description
    • 30.10.5 ATM Controller Buffer Descriptors (BDs)
      • 30.10.5.1 Transmit Buffer Operation
        • Figure 30-41. Transmit Buffers and BD Table Example
      • 30.10.5.2 Receive Buffer Operation
        • 30.10.5.2.1 Static Buffer Allocation
          • Figure 30-42. Receive Static Buffer Allocation Example
        • 30.10.5.2.2 Global Buffer Allocation
          • Figure 30-43. Receive Global Buffer Allocation Example
        • 30.10.5.2.3 Free Buffer Pools
          • Figure 30-44. Free Buffer Pool Structure
          • Figure 30-45. Free Buffer Pool Entry
          • Table 30-32. Free Buffer Pool Entry Field Descriptions
        • 30.10.5.2.4 Free Buffer Pool Parameter Tables
          • Table 30-33. Free Buffer Pool Parameter Table (continued)
      • 30.10.5.3 ATM Controller Buffers
        • Table 30-34. Receive and Transmit Buffers
      • 30.10.5.4 AAL5 RxBD
        • Figure 30-46. AAL5 RxBD
        • Table 30-35. AAL5 RxBD Field Descriptions (continued)
      • 30.10.5.5 AAL1 RxBD
        • Figure 30-47. AAL1 RxBD
        • Table 30-36. AAL1 RxBD Field Descriptions
      • 30.10.5.6 AAL0 RxBD
        • Figure 30-48. AAL0 RxBD
        • Table 30-37. AAL0 RxBD Field Descriptions
      • 30.10.5.7 AAL1 CES RxBD
      • 30.10.5.8 AAL2 RxBD
      • 30.10.5.9 AAL5, AAL1 CES User-Defined Cell-RxBD Extension
        • Figure 30-49. User-Defined Cell-RxBD Extension
      • 30.10.5.10 AAL5 TxBDs
        • Figure 30-50. AAL5 TxBD
        • Table 30-38. AAL5 TxBD Field Descriptions
      • 30.10.5.11 AAL1 TxBDs
        • Figure 30-51. AAL1 TxBD
        • Table 30-39. AAL1 TxBD Field Descriptions
      • 30.10.5.12 AAL0 TxBDs
        • Figure 30-52. AAL0 TxBDs
        • Table 30-40. AAL0 TxBD Field Descriptions
      • 30.10.5.13 AAL1 CES TxBDs
      • 30.10.5.14 AAL2 TxBDs
      • 30.10.5.15 AAL5, AAL1 User-Defined Cell-TxBD Extension
        • Figure 30-53. User-Defined Cell-TxBD Extension
    • 30.10.6 AAL1 Sequence Number (SN) Protection Table
      • Figure 30-54. AAL1 Sequence Number (SN) Protection Table
    • 30.10.7 UNI Statistics Table
      • Table 30-41. UNI Statistics Table
  • 30.11 ATM Exceptions
    • 30.11.1 Interrupt Queues
      • Figure 30-55. Interrupt Queue Structure
    • 30.11.2 Interrupt Queue Entry
      • Figure 30-56. Interrupt Queue Entry
      • Table 30-42. Interrupt Queue Entry Field Description
    • 30.11.3 Interrupt Queue Parameter Tables
      • Table 30-43. Interrupt Queue Parameter Table (continued)
  • 30.12 The UTOPIA Interface
    • 30.12.1 UTOPIA Interface Master Mode
      • Figure 30-57. UTOPIA Master Mode Signals
      • Table 30-44. UTOPIA Master Mode Signal Descriptions (continued)
      • 30.12.1.1 UTOPIA Master Multiple PHY Operation
    • 30.12.2 UTOPIA Interface Slave Mode
      • Figure 30-58. UTOPIA Slave Mode Signals
      • Table 30-45. UTOPIA Slave Mode Signals (continued)
      • 30.12.2.1 UTOPIA Slave Multiple PHY Operation
      • 30.12.2.2 UTOPIA Clocking Modes
      • 30.12.2.3 UTOPIA Loop-Back Modes
        • Table 30-46. UTOPIA Loop-Back Modes
  • 30.13 ATM Registers
    • 30.13.1 General FCC Mode Register (GFMR)
    • 30.13.2 FCC Protocol-Specific Mode Register (FPSMR)
      • Figure 30-59. FCC ATM Mode Register (FPSMR)
      • Table 30-47. FCC ATM Mode Register (FPSMR) (continued)
    • 30.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
      • Figure 30-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)
      • Table 30-48. FCCE/FCCM Field Descriptions
    • 30.13.4 FCC Transmit Internal Rate Registers (FTIRRx) (FCC1 and FCC2 Only)
      • Figure 30-61. FCC Transmit Internal Rate Registers (FTIRRx)
      • Table 30-49. FTIRRx Field Descriptions
      • Figure 30-62. FCC Transmit Internal Rate Clocking
  • 30.14 ATM Transmit Command
    • Figure 30-63. COMM_INFO Field
    • Table 30-50. COMM_INFO Field Descriptions
  • 30.15 SRTS Generation and Clock Recovery Using External Logic
    • Figure 30-64. AAL1 CES SRTS Generation Using External Logic
    • Figure 30-65. AAL1 CES SRTS Clock Recovery Using External Logic
  • 30.16 Configuring the ATM Controller for Maximum CPM Performance
    • 30.16.1 Using Transmit Internal Rate Mode
    • 30.16.2 APC Configuration
    • 30.16.3 Buffer Configuration
• Chapter 31 ATM AAL1 Circuit Emulation Service
  • 31.1 Features
  • 31.2 AAL1 CES Transmitter Overview
    • 31.2.1 Data Path
      • Figure 31-1. AAL1 Transmit Cell Format
      • Figure 31-2. AAL1 SDT Cells Type
    • 31.2.2 Signaling Path
      • Figure 31-3. AAL1 Framing Formats
  • 31.3 AAL1 CES Receiver Overview
    • Figure 31-4. AAL1 CES Receiver Data flow
  • 31.4 Interworking Functions
    • 31.4.1 Automatic Data Forwarding
      • 31.4.1.1 ATM-to-TDM
        • Figure 31-5. ATM-to-TDM Interworking
      • 31.4.1.2 TDM-to-ATM
        • Figure 31-6. TDM-to-ATM Interworking
    • 31.4.2 Timing Issues
    • 31.4.3 Clock Synchronization (SRTS, Adaptive FIFO)
    • 31.4.4 Mapping TDM Time Slots to VCs
    • 31.4.5 Trunk Condition
    • 31.4.6 Channel Associated Signaling (CAS) Support
      • Figure 31-7. Mapping CAS Data on a Serial Interface
      • Figure 31-8. Internal CAS Block Formats
    • 31.4.7 Mapping VC Signaling to CAS Blocks
      • Figure 31-9. Mapping CAS Entry
      • 31.4.7.1 CAS Routing Table
        • Figure 31-10. AAL1 CES CAS Routing Table (CRT)
        • Figure 31-11. AAL1 CES CAS Routing Table Entry
        • Table 31-1. CAS Routing Table Entry Field Descriptions
      • 31.4.7.2 TDM-to-ATM CAS Support
        • Figure 31-12. CAS Flow TDM-to-ATM
        • 31.4.7.2.1 CAS Mapping Using the Core (Optional)
      • 31.4.7.3 ATM-to-TDM CAS Support
        • Figure 31-13. CAS Flow ATM-to-TDM
        • 31.4.7.3.1 CAS Updates Using the Core (Optional)
  • 31.5 ATM-to-TDM Adaptive Slip Control
    • Figure 31-14. Data Structure for ATM-to-TDM Adaptive Slip Control
    • 31.5.1 CES Adaptive Threshold Tables
      • Figure 31-15. CES Adaptive Threshold Table
      • Table 31-2. CES Adaptive Threshold Table Field Descriptions
      • Figure 31-16. Pre-Underrun Sequence
      • Figure 31-17. Pre-Overrun Sequence
  • 31.6 3-Step-SN Algorithm
    • 31.6.1 The Three States of the Algorithm
      • Figure 31-18. Recoverable Sync Fail sequence options
      • Figure 31-19. 3-Step-SN-Algorithm
  • 31.7 Pointer Verification Mechanism
    • Figure 31-20. Pointer verification mechanism
  • 31.8 AAL-1 Memory Structure
    • 31.8.1 AAL1 CES Parameter RAM
      • Table 31-3. AAL1 CES Field Descriptions (continued)
      • Table 31-4. AAL1 CES Parameters
  • 31.9 Receive and Transmit Connection Tables (RCT, TCT)
    • 31.9.1 Receive Connection Table (RCT)
      • Figure 31-21. Receive Connection Table (RCT) Entry
      • Table 31-5. RCT Field Descriptions (continued)
      • 31.9.1.1 AAL1 CES Protocol-Specific RCT
        • Figure 31-22. AAL1 CES Protocol-Specific RCT
        • Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued)
    • 31.9.2 Transmit Connection Table (TCT)
      • Figure 31-23. Transmit Connection Table (TCT) Entry
      • Table 31-7. TCT Field Descriptions (continued)
      • 31.9.2.1 AAL1 CES Protocol-Specific TCT
        • Figure 31-24. AAL1 CES Protocol-Specific TCT
        • Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions (continued)
  • 31.10 Outgoing CAS Status Register (OCASSR)
    • Figure 31-25. Outgoing CAS Status Register (OCASSR)
    • Table 31-9. OCASSR Field Descriptions
  • 31.11 Buffer Descriptors
    • 31.11.1 Transmit Buffer Operation
      • Figure 31-26. Transmit Buffers and BD Table Example
    • 31.11.2 Receive Buffer Operation
      • Figure 31-27. Receive Buffers and BD Table Example
  • 31.12 ATM Controller Buffers
    • Table 31-10. Receive and Transmit Buffers
    • 31.12.1 AAL1 CES RxBD
      • Figure 31-28. AAL1 CES RxBD
      • Table 31-11. AAL1 CES RxBD Field Descriptions
    • 31.12.2 AAL1 CES TxBDs
      • Figure 31-29. AAL1 CES TxBD
      • Table 31-12. AAL1 CES TxBD Field Descriptions (continued)
  • 31.13 AAL1 CES Exceptions
    • 31.13.1 AAL1 CES Interrupt Queue Entry
      • Figure 31-30. AAL1 CES Interrupt Queue Entry
      • Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions (continued)
  • 31.14 AAL1 Sequence Number (SN) Protection Table
    • Figure 31-31. AAL1 Sequence Number (SN) Protection Table
  • 31.15 Internal AAL1 CES Statistics Tables
    • Table 31-14. AAL1 CES DPR Statistics Table
  • 31.16 External AAL1 CES Statistics Tables
    • Table 31-15. AAL1 CES External Statistics Table
  • 31.17 CES-Specific Additions to the MCC
  • 31.18 Application Considerations
    • Figure 31-32. TDM-to-ATM Timing Issue
• Chapter 32 ATM AAL2
  • 32.1 Introduction
    • Figure 32-1. AAL2 Data Units
    • Figure 32-2. AAL2 Sublayer Structure
    • Figure 32-3. AAL2 Switching Example
  • 32.2 Features
  • 32.3 AAL2 Transmitter
    • 32.3.1 Transmitter Overview
    • 32.3.2 Transmit Priority Mechanism
      • 32.3.2.1 Round Robin Priority
        • Figure 32-4. Round Robin Priority
      • 32.3.2.2 Fixed Priority
        • Figure 32-5. Fixed Priority Mode
    • 32.3.3 Partial Fill Mode (PFM)
    • 32.3.4 No STF Mode
    • 32.3.5 AAL2 Tx Data Structures
      • 32.3.5.1 AAL2 Protocol-Specific TCT
        • Figure 32-6. AAL2 Protocol-Specific Transmit Connection Table (TCT)
        • Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued)
      • 32.3.5.2 CPS Tx Queue Descriptor
        • Figure 32-7. CPS Tx Queue Descriptor (TxQD)
        • Table 32-2. CPS TxQD Field Descriptions (continued)
      • 32.3.5.3 CPS Buffer Structure
        • Figure 32-8. Buffer Structure Example for CPS Packets
        • Figure 32-9. CPS TxBD
        • Table 32-3. CPS TxBD Field Descriptions
        • Figure 32-10. CPS Packet Header Format
      • 32.3.5.4 SSSAR Tx Queue Descriptor
        • Figure 32-11. SSSAR Tx Queue Descriptor
        • Table 32-4. SSSAR TxQD Field Descriptions
      • 32.3.5.5 SSSAR Transmit Buffer Descriptor
        • Figure 32-12. SSSAR TxBD
        • Table 32-5. SSSAR TxBD Field Descriptions (continued)
  • 32.4 AAL2 Receiver
    • 32.4.1 Receiver Overview
    • 32.4.2 Mapping of PHY | VP | VC | CID
      • Figure 32-13. CID Mapping Process
    • 32.4.3 AAL2 Switching
      • Figure 32-14. AAL2 Switching
    • 32.4.4 AAL2 RX Data Structures
      • 32.4.4.1 AAL2 Protocol-Specific RCT
        • Figure 32-15. AAL2 Protocol-Specific Receive Connection Table (RCT)
        • Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions
      • 32.4.4.2 CID Mapping Tables and RxQDs
      • 32.4.4.3 CPS Rx Queue Descriptors
        • Figure 32-16. CPS Rx Queue Descriptor
        • Table 32-7. CPS RxQD Field Descriptions
      • 32.4.4.4 CPS Receive Buffer Descriptor (RxBD)
        • Figure 32-17. CPS Receive Buffer Descriptor
        • Table 32-8. CPS RxBD Field Descriptions
      • 32.4.4.5 CPS Switch Rx Queue Descriptor
        • Figure 32-18. CPS Switch Rx Queue Descriptor
        • Table 32-9. CPS Switch RxQD Field Descriptions
      • 32.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD)
        • Figure 32-19. Switch Receive/Transmit Buffer Descriptor
        • Table 32-10. Switch RxBD Field Descriptions
      • 32.4.4.7 SSSAR Rx Queue Descriptor
        • Figure 32-20. SSSAR Rx Queue Descriptor
        • Table 32-11. SSSAR RxQD Field Descriptions (continued)
      • 32.4.4.8 SSSAR Receive Buffer Descriptor
        • Figure 32-21. SSSAR Receive Buffer Descriptor
        • Table 32-12. SSSAR RxBD Field Descriptions
  • 32.5 AAL2 Parameter RAM
    • Table 32-13. AAL2 Parameter RAM (continued)
  • 32.6 User-Defined Cells in AAL2
    • Figure 32-22. UDC Header Table
  • 32.7 AAL2 Exceptions
    • Figure 32-23. AAL2 Interrupt Queue Entry CID ¹ 0
    • Table 32-14. AAL2 Interrupt Queue Entry CID ¹ 0 Field Descriptions
    • Figure 32-24. AAL2 Interrupt Queue Entry CID = 0
    • Table 32-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions
• Chapter 33 Inverse Multiplexing for ATM (IMA)
  • 33.1 Features
    • Table 33-1. IMA Sublayer in Layer Reference Model
    • 33.1.1 References
    • 33.1.2 IMA Versions Supported
    • 33.1.3 PowerQUICC II Versions Supported
    • 33.1.4 PHY-Layer Devices Supported
    • 33.1.5 ATM Features Not Supported
    • 33.1.6 Additional Impact on PowerQUICC II Features
  • 33.2 IMA Protocol Overview
    • 33.2.1 Introduction
      • Figure 33-1. Basic Concept of IMA
    • 33.2.2 IMA Frame Overview
      • Figure 33-2. Illustration of IMA Frames
      • Figure 33-3. IMA Microcode Overview
    • 33.2.3 Overview of IMA Cells
      • 33.2.3.1 IMA Control Cells
        • Figure 33-4. IMA Frame and ICP Cell Formats
      • 33.2.3.2 IMA Filler Cells
  • 33.3 IMA Microcode Architecture
    • 33.3.1 IMA Function Partitioning
      • 33.3.1.1 User Plane Functions Performed by Microcode
      • 33.3.1.2 Plane Management Functions Performed by Microcode
    • 33.3.2 Transmit Architecture
      • Figure 33-5. IMA Transmit Task Interaction
      • 33.3.2.1 TRL Operation
        • 33.3.2.1.1 TRL Service Latency
      • 33.3.2.2 Non-TRL Operation
      • 33.3.2.3 Transmit Queue Operation Examples (ITC mode)
        • Figure 33-6. Transmit Queue Normal Operating State
        • Figure 33-7. Transmit Queue Behavior: Link Clock Rate Same as TRL
        • Figure 33-8. Transmit Queue Behavior: Link Clock Rate Slower than TRL
        • Figure 33-9. Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence
      • 33.3.2.4 Differences in CTC Operation
    • 33.3.3 Receive Architecture
      • Figure 33-10. IMA Receive Task Interaction
      • 33.3.3.1 Cell Reception Task
        • Figure 33-11. IMA Microcode: Receive Process
      • 33.3.3.2 Cell Processing Activation Function
        • 33.3.3.2.1 On-Demand Cell Processing
        • 33.3.3.2.2 IDCR-Regulated Cell Processing
      • 33.3.3.3 Cell Processing Task
  • 33.4 IMA Programming Model
    • 33.4.1 Data Structure Organization
      • Figure 33-12. IMA Root Table Data Structures
    • 33.4.2 IMA FCC Programming
      • 33.4.2.1 FCC Registers
        • 33.4.2.1.1 FPSMRx
        • 33.4.2.1.2 FTIRRx
      • 33.4.2.2 FCC Parameters
        • 33.4.2.2.1 TCELL_TMP_BASE and RCELL_TMP_BASE
        • 33.4.2.2.2 GMODE
      • 33.4.2.3 IMA-Specific FCC Parameters
        • Table 33-2. FCC Parameter RAM Additions
    • 33.4.3 IMA Root Table
      • Table 33-3. IMA Root Table (continued)
      • 33.4.3.1 IMA Control (IMACNTL)
        • Figure 33-13. IMA Control (IMACNTL)
        • Table 33-4. IMACNTL Field Descriptions
    • 33.4.4 IMA Group Tables
      • 33.4.4.1 IMA Group Transmit Table Entry
        • Table 33-5. IMA Group Transmit Table Entry (continued)
        • 33.4.4.1.1 IMA Group Transmit Control (IGTCNTL)
          • Figure 33-14. IMA Group Transmit Control (IGTCNTL)
          • Table 33-6. IGTCNTL Field Descriptions
        • 33.4.4.1.2 IMA Group Transmit State (IGTSTATE)
          • Figure 33-15. IMA Group Transmit State (IGTSTATE)
          • Table 33-7. IGTSTATE Field Descriptions
        • 33.4.4.1.3 Transmit Group Order Table
          • Figure 33-16. Transmit Group Order Table Entry
          • Table 33-8. Transmit Group Order Table Entry Field Descriptions
        • 33.4.4.1.4 ICP Cell Templates
          • Table 33-9. ICP Cell Template (continued)
      • 33.4.4.2 IMA Group Receive Table Entry
        • Table 33-10. IMA Group Receive Table Entry (continued)
        • 33.4.4.2.1 IMA Group Receive Control (IGRCNTL)
          • Figure 33-17. IMA Group Receive Control (IGRCNTL)
          • Table 33-11. IGRCNTL Field Descriptions
        • 33.4.4.2.2 IMA Group Receive State (IGRSTATE)
          • Figure 33-18. IMA Group Receive State (IGRSTATE)
          • Table 33-12. IGRSTATE Field Descriptions
        • 33.4.4.2.3 IMA Receive Group Frame Size
          • Figure 33-19. IMA Receive Group Frame Size (IGRSTATE)
          • Table 33-13. IRGFS Field Descriptions
        • 33.4.4.2.4 Receive Group Order Tables
          • Figure 33-20. Receive Group Order Table Entry
          • Table 33-14. Receive Group Order Table Entry Field Descriptions
    • 33.4.5 IMA Link Tables
      • 33.4.5.1 IMA Link Transmit Table Entry
        • Table 33-15. IMA Link Transmit Table Entry (continued)
        • 33.4.5.1.1 IMA Link Transmit Control (ILTCNTL)
          • Figure 33-21. IMA Link Transmit Control (ILTCNTL)
          • Table 33-16. ILTCNTL Field Descriptions (continued)
        • 33.4.5.1.2 IMA Link Transmit State (ILTSTATE)
          • Figure 33-22. IMA Link Transmit State (ILTSTATE)
          • Table 33-17. ILTSTATE Field Descriptions
        • 33.4.5.1.3 IMA Transmit Interrupt Status (ITINTSTAT)
          • Figure 33-23. IMA Transmit Interrupt Status (ITINTSTAT)
          • Table 33-18. ITINTSTAT Field Descriptions
      • 33.4.5.2 IMA Link Receive Table Entry
        • Table 33-19. IMA Link Receive Table Entry (continued)
        • 33.4.5.2.1 IMA Link Receive Control (ILRCNTL)
          • Figure 33-24. IMA Link Receive Control (ILRCNTL)
          • Table 33-20. ILRCNTL Field Descriptions
        • 33.4.5.2.2 IMA Link Receive State (ILRSTATE)
          • Figure 33-25. IMA Link Receive State (ILRSTATE)
          • Table 33-21. ILRSTATE Field Descriptions
      • 33.4.5.3 IMA Link Receive Statistics Table
        • Table 33-22. IMA Link Receive Statistics Table Entry
    • 33.4.6 Structures in External Memory
      • 33.4.6.1 Transmit Queues
        • Figure 33-26. IMA Transmit Queue
      • 33.4.6.2 Delay Compensation Buffers (DCB)
        • Figure 33-27. Cell Buffer in Delay Compensation Buffer
        • Figure 33-28. IMA Delay Compensation Buffer
    • 33.4.7 IMA Exceptions
      • 33.4.7.1 IMA Interrupt Queue Entry
        • Figure 33-29. IMA Interrupt Queue Entry
        • Table 33-23. IMA Interrupt Queue Entry Field Descriptions
      • 33.4.7.2 ICP Cell Reception Exceptions
    • 33.4.8 IDCR Timer Programming
      • 33.4.8.1 IDCR Master Clock
      • 33.4.8.2 IDCR FCC Parameter Shadow
        • 33.4.8.2.1 PowerQUICC II Features Unavailable if IDCR is Used
          • Table 33-24. Unavailable Features when DREQx used as IDCR Master Clock
        • 33.4.8.2.2 Programming the FCC Parameter Shadow
        • 33.4.8.2.3 On-the-Fly Changes of FCC Parameters
      • 33.4.8.3 IDCR_Init Command
      • 33.4.8.4 IDCR Root Parameters
        • Table 33-25. IDCR IMA Root Parameters
      • 33.4.8.5 IDCR Table Entry
        • Table 33-26. IDCR Table Entry
      • 33.4.8.6 IDCR Counter Algorithm
      • 33.4.8.7 IDCR Events
        • Figure 33-30. IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR)
        • Table 33-27. IDSR/IDMR Field Descriptions (continued)
    • 33.4.9 APC Programming for IMA
      • Table 33-28. Examples of APC Programming for IMA
      • 33.4.9.1 Programming for CBR, UBR, VBR, and UBR+
      • 33.4.9.2 Programming for ABR
    • 33.4.10 Changing IMA Version
      • Figure 33-31. COMM_INFO Field
      • Table 33-29. COMM_INFO Field Descriptions
  • 33.5 IMA Software Interface and Requirements
    • 33.5.1 Software Model
      • Figure 33-32. IMA Microcode/Software Interaction
    • 33.5.2 Initialization Procedure
    • 33.5.3 Software Responsibilities
      • 33.5.3.1 System Definition
      • 33.5.3.2 General Operation
      • 33.5.3.3 Receive Link State Machine Control
      • 33.5.3.4 Receive Group State Machine Control
      • 33.5.3.5 Transmit Link State Machine Control
      • 33.5.3.6 Transmit Group State Machine Control
      • 33.5.3.7 Group Symmetry Control
      • 33.5.3.8 ICP End-to-End Channel Transmission
      • 33.5.3.9 Link Addition and Slow Recovery (LASR) Procedure
      • 33.5.3.10 Failure Alarms
      • 33.5.3.11 Test Pattern Control
      • 33.5.3.12 Performance Parameter Measurement and Reporting
      • 33.5.3.13 SNMP MIBs
    • 33.5.4 IMA Software Procedures
      • 33.5.4.1 Transmit ICP Cell Signalling
      • 33.5.4.2 Receive Link Start-up Procedure
      • 33.5.4.3 Group Start-up Procedure
        • 33.5.4.3.1 As Initiator (TX)
          • Figure 33-33. Near-End versus Far-End
        • 33.5.4.3.2 As Responder (RX)
      • 33.5.4.4 Link Addition Procedure
        • 33.5.4.4.1 Rx Steps
        • 33.5.4.4.2 TX Parameters
      • 33.5.4.5 Link Removal Procedure
        • 33.5.4.5.1 Rx Steps
        • 33.5.4.5.2 TX Parameters
      • 33.5.4.6 Link Receive Deactivation Procedure
      • 33.5.4.7 Link Receive Reactivation Procedure
      • 33.5.4.8 TRL On-the-Fly Change Procedure
      • 33.5.4.9 Transmit Event Response Procedures
      • 33.5.4.10 Receive Event Response Procedures
      • 33.5.4.11 Test Pattern Procedure
        • 33.5.4.11.1 As Initiator (NE)
        • 33.5.4.11.2 As Responder (FE)
      • 33.5.4.12 IDCR Operation
        • 33.5.4.12.1 IDCR Start-up
        • 33.5.4.12.2 Activating a Group in IDCR Mode
      • 33.5.4.13 End-to-End Channel Signalling Procedure
        • 33.5.4.13.1 Transmit
        • 33.5.4.13.2 Receive
• Chapter 34 ATM Transmission Convergence Layer
  • Figure 34-1. Serial ATM Using FCC2 and TC Blocks (Single Channel)
  • 34.1 Features
  • 34.2 Functionality
    • Figure 34-2. TC Layer Block Diagram
    • 34.2.1 Receive ATM Cell Functions
      • Figure 34-3. TC Cell Delineation State Machine
      • Figure 34-4. HEC: Receiver Modes of Operation
      • 34.2.1.1 Receive ATM 2-Cell FIFO
    • 34.2.2 Transmit ATM Cell Functions
      • 34.2.2.1 Transmit ATM 2-Cell FIFO
    • 34.2.3 Receive UTOPIA Interface
    • 34.2.4 Transmit UTOPIA Interface
  • 34.3 Signals
    • Table 34-1. TC Layer Signals
  • 34.4 TC Layer Programming Mode
    • 34.4.1 TC Layer Registers
      • 34.4.1.1 TC Layer Mode Register [1-8] (TCMODEx)
        • Figure 34-5. TC Layer Mode Register (TCMODEx)
        • Table 34-2. TCMODEx Field Descriptions (continued)
      • 34.4.1.2 Cell Delineation State Machine Register [1-8] (CDSMRx)
        • Figure 34-6. Cell Delineation State Machine Register (CDSMRx)
        • Table 34-3. CDSMRx Field Descriptions
      • 34.4.1.3 TC Layer Event Register [1-8] (TCERx)
        • Figure 34-7. TC Layer Event Register (TCERx)
        • Table 34-4. TCERx Field Descriptions
      • 34.4.1.4 TC Layer Mask Register (TCMRx)
    • 34.4.2 TC Layer General Registers
      • 34.4.2.1 TC Layer General Event Register (TCGER)
        • Figure 34-8. TC Layer General Event Register (TCGER)
        • Table 34-5. TCGER Field Descriptions
      • 34.4.2.2 TC Layer General Status Register (TCGSR)
        • Figure 34-9. TC Layer General Status Register (TCGSR)
        • Table 34-6. TCGSR Field Descriptions
    • 34.4.3 TC Layer Cell Counters
      • 34.4.3.1 Received Cell Counter [1-8] (TC_RCCx)
      • 34.4.3.2 Transmitted Cell Counter [1-8] (TC_TCCx)
      • 34.4.3.3 Errored Cell Counter [1-8] (TC_ECCx)
      • 34.4.3.4 Corrected Cell Counter [1-8] (TC_CCCx)
      • 34.4.3.5 Transmitted IDLE Cell Counter [1-8] (TC_ICCx)
      • 34.4.3.6 Filtered Cell Counter [1-8] (TC_FCCx)
    • 34.4.4 Programming FCC2
    • 34.4.5 Programming and Operating the TC Layer
      • 34.4.5.1 Receive
      • 34.4.5.2 Transmit
        • Figure 34-10. TC Operation in FCC External Rate Mode
        • Figure 34-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)
  • 34.5 Implementation Example
    • Figure 34-12. Example of Serial ATM Application
    • 34.5.1 Operating the TC Layer at Higher Frequencies
    • 34.5.2 Programming a T1 Application
    • Step 1
      • Table 34-7. Programming GFMR and FPSMR to Setup the FCC2
    • Step 2
    • Step 3
      • Table 34-8. Enable FCC2
    • Step 4
      • Table 34-9. Programming the CPM MUX for a TI Application
    • Step 5
      • Table 34-10. Programming the TC Layer Block
    • Step 6
      • Table 34-11. Programming the SI RAM (Rx or Tx) for a T1 Application
    • Step 7
      • Table 34-12. Programming SI Registers to Enable TDM
• Chapter 35 Fast Ethernet Controller
  • Figure 35-1. Ethernet Frame Structure
  • 35.1 Fast Ethernet on the PowerQUICC II
    • Figure 35-2. Ethernet Block Diagram
  • 35.2 Features
  • 35.3 Connecting the PowerQUICC II to Fast Ethernet
    • Figure 35-3. Connecting the PowerQUICC II to Ethernet
  • 35.4 Ethernet Channel Frame Transmission
  • 35.5 Ethernet Channel Frame Reception
  • 35.6 Flow Control
    • Table 35-1. Flow Control Frame Structure
  • 35.7 CAM Interface
  • 35.8 Ethernet Parameter RAM
    • Table 35-2. Ethernet-Specific Parameter RAM (continued)
  • 35.9 Programming Model
  • 35.10 Ethernet Command Set
    • Table 35-3. Transmit Commands
    • Table 35-4. Receive Commands
  • 35.11 RMON Support
    • Table 35-5. RMON Statistics and Counters (continued)
  • 35.12 Ethernet Address Recognition
    • Figure 35-4. Ethernet Address Recognition Flowchart
  • 35.13 Hash Table Algorithm
  • 35.14 Interpacket Gap Time
  • 35.15 Handling Collisions
  • 35.16 Internal and External Loopback
  • 35.17 Ethernet Error-Handling Procedure
    • Table 35-6. Transmission Errors
    • Table 35-7. Reception Errors
  • 35.18 Fast Ethernet Registers
    • 35.18.1 FCC Ethernet Mode Register (FPSMR)
      • Figure 35-5. FCC Ethernet Mode Registers (FPSMR)
      • Table 35-8. FPSMR Ethernet Field Descriptions (continued)
    • 35.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
      • Figure 35-6. Ethernet Event Register (FCCE)/Mask Register (FCCM)
      • Table 35-9. FCCE/FCCM Field Descriptions
      • Figure 35-7. Ethernet Interrupt Events Example
  • 35.19 Ethernet RxBDs
    • Figure 35-8. Fast Ethernet Receive Buffer (RxBD)
    • Table 35-10. RxBD Field Descriptions (continued)
    • Figure 35-9. Ethernet Receiving Using RxBDs
  • 35.20 Ethernet TxBDs
    • Figure 35-10. Fast Ethernet Transmit Buffer (TxBD)
    • Table 35-11. Ethernet TxBD Field Definitions (continued)
• Chapter 36 FCC HDLC Controller
  • 36.1 Key Features
  • 36.2 HDLC Channel Frame Transmission Processing
    • Figure 36-1. HDLC Framing Structure
  • 36.3 HDLC Channel Frame Reception Processing
  • 36.4 HDLC Parameter RAM
    • Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map (continued)
    • Figure 36-2. HDLC Address Recognition Example
  • 36.5 Programming Model
    • 36.5.1 HDLC Command Set
      • Table 36-2. Transmit Commands (continued)
      • Table 36-3. Receive Commands
    • 36.5.2 HDLC Error Handling
      • Table 36-4. HDLC Transmission Errors
      • Table 36-5. HDLC Reception Errors
  • 36.6 HDLC Mode Register (FPSMR)
    • Figure 36-3. HDLC Mode Register (FPSMR)
    • Table 36-6. FPSMR Field Descriptions (continued)
  • 36.7 HDLC Receive Buffer Descriptor (RxBD)
    • Figure 36-4. FCC HDLC Receiving Using RxBDs
    • Figure 36-5. FCC HDLC Receive Buffer Descriptor (RxBD)
    • Table 36-7. RxBD field Descriptions (continued)
  • 36.8 HDLC Transmit Buffer Descriptor (TxBD)
    • Figure 36-6. FCC HDLC Transmit Buffer Descriptor (TxBD)
    • Table 36-8. HDLC TxBD Field Descriptions
  • 36.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
    • Figure 36-7. HDLC Event Register (FCCE)/Mask Register (FCCM)
    • Table 36-9. FCCE/FCCM Field Descriptions
    • Figure 36-8. HDLC Interrupt Event Example
  • 36.10 FCC Status Register (FCCS)
    • Figure 36-9. FCC Status Register (FCCS)
    • Table 36-10. FCCS Register Field Descriptions
• Chapter 37 FCC Transparent Controller
  • 37.1 Features
  • 37.2 Transparent Channel Operation
  • 37.3 Achieving Synchronization in Transparent Mode
    • 37.3.1 In-Line Synchronization Pattern
      • Figure 37-1. In-Line Synchronization Pattern
    • 37.3.2 External Synchronization Signals
    • 37.3.3 Transparent Synchronization Example
      • Figure 37-2. Sending Transparent Frames between PowerQUICC IIs
• Chapter 38 Serial Peripheral Interface (SPI)
  • Figure 38-1. SPI Block Diagram
  • 38.1 Features
  • 38.2 SPI Clocking and Signal Functions
  • 38.3 Configuring the SPI Controller
    • 38.3.1 The SPI as a Master Device
      • Figure 38-2. Single-Master/Multi-Slave Configuration
    • 38.3.2 The SPI as a Slave Device
    • 38.3.3 The SPI in Multimaster Operation
      • Figure 38-3. Multimaster Configuration
  • 38.4 Programming the SPI Registers
    • 38.4.1 SPI Mode Register (SPMODE)
      • Figure 38-4. SPMODE-SPI Mode Register
      • Table 38-1. SPMODE Field Descriptions (continued)
      • Figure 38-5. SPI Transfer Format with SPMODE[CP] = 0
      • Figure 38-6. SPI Transfer Format with SPMODE[CP] = 1
      • 38.4.1.1 SPI Examples with Different SPMODE[LEN] Values
        • Table 38-2. Example Conventions
    • 38.4.2 SPI Event/Mask Registers (SPIE/SPIM)
      • Figure 38-7. SPIE/SPIM-SPI Event/Mask Registers
      • Table 38-3. SPIE/SPIM Field Descriptions
    • 38.4.3 SPI Command Register (SPCOM)
      • Figure 38-8. SPCOM-SPI Command Register
      • Table 38-4. SPCOM Field Descriptions
  • 38.5 SPI Parameter RAM
    • Table 38-5. SPI Parameter RAM Memory Map
    • 38.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)
      • Figure 38-9. RFCR/TFCR-Function Code Registers
      • Table 38-6. RFCR/TFCR Field Descriptions
  • 38.6 SPI Commands
    • Table 38-7. SPI Commands (continued)
  • 38.7 The SPI Buffer Descriptor (BD) Table
    • Figure 38-10. SPI Memory Structure
    • 38.7.1 SPI Buffer Descriptors (BDs)
      • 38.7.1.1 SPI Receive BD (RxBD)
        • Figure 38-11. SPI RxBD
        • Table 38-8. SPI RxBD Status and Control Field Descriptions (continued)
      • 38.7.1.2 SPI Transmit BD (TxBD)
        • Figure 38-12. SPI TxBD
        • Table 38-9. SPI TxBD Status and Control Field Descriptions (continued)
  • 38.8 SPI Master Programming Example
  • 38.9 SPI Slave Programming Example
  • 38.10 Handling Interrupts in the SPI
• Chapter 39 I2C Controller
  • Figure 39-1. I2C Controller Block Diagram
  • 39.1 Features
  • 39.2 I2C Controller Clocking and Signal Functions
    • Figure 39-2. I2C Master/Slave General Configuration
  • 39.3 I2C Controller Transfers
    • Figure 39-3. I2C Transfer Timing
    • 39.3.1 I2C Master Write (Slave Read)
      • Figure 39-4. I2C Master Write Timing
    • 39.3.2 I2C Loopback Testing
    • 39.3.3 I2C Master Read (Slave Write)
      • Figure 39-5. I2C Master Read Timing
    • 39.3.4 I2C Multi-Master Considerations
  • 39.4 I2C Registers
    • 39.4.1 I2C Mode Register (I2MOD)
      • Figure 39-6. I2C Mode Register (I2MOD)
      • Table 39-1. II2MOD Field Descriptions
    • 39.4.2 I2C Address Register (I2ADD)
      • Figure 39-7. I2C Address Register (I2ADD)
      • Table 39-2. I2ADD Field Descriptions
    • 39.4.3 I2C Baud Rate Generator Register (I2BRG)
      • Figure 39-8. I2C Baud Rate Generator Register (I2BRG)
      • Table 39-3. I2BRG Field Descriptions
    • 39.4.4 I2C Event/Mask Registers (I2CER/I2CMR)
      • Figure 39-9. I2C Event/Mask Registers (I2CER/I2CMR)
      • Table 39-4. I2CER/I2CMR Field Descriptions
    • 39.4.5 I2C Command Register (I2COM)
      • Figure 39-10. I2C Command Register (I2COM)
      • Table 39-5. I2COM Field Descriptions
  • 39.5 I2C Parameter RAM
    • Table 39-6. I2C Parameter RAM Memory Map (continued)
    • Figure 39-11. I2C Function Code Registers (RFCR/TFCR)
    • Table 39-7. RFCR/TFCR Field Descriptions
  • 39.6 I2C Commands
    • Table 39-8. I2C Transmit/Receive Commands
  • 39.7 The I2C Buffer Descriptor (BD) Table
    • Figure 39-12. I2C Memory Structure
    • 39.7.1 I2C Buffer Descriptors (BDs)
      • 39.7.1.1 I2C Receive Buffer Descriptor (RxBD)
        • Figure 39-13. I2C RxBD
        • Table 39-9. I2C RxBD Status and Control Bits
      • 39.7.1.2 I2C Transmit Buffer Descriptor (TxBD)
        • Figure 39-14. I2C TxBD
        • Table 39-10. I2C TxBD Status and Control Bits
• Chapter 40 Parallel I/O Ports
  • 40.1 Features
  • 40.2 Port Registers
    • 40.2.1 Port Open-Drain Registers (PODRA-PODRD)
      • Figure 40-1. Port Open-Drain Registers (PODRA-PODRD)
      • Table 40-1. PODRx Field Descriptions
    • 40.2.2 Port Data Registers (PDATA-PDATD)
      • Figure 40-2. Port Data Registers (PDATA-PDATD)
    • 40.2.3 Port Data Direction Registers (PDIRA-PDIRD)
      • Figure 40-3. Port Data Direction Register (PDIR)
      • Table 40-2. PDIR Field Descriptions
    • 40.2.4 Port Pin Assignment Register (PPAR)
      • Figure 40-4. Port Pin Assignment Register (PPARA-PPARD)
      • Table 40-3. PPAR Field Descriptions
    • 40.2.5 Port Special Options Registers A-D (PSORA-PSORD)
      • Figure 40-5. Special Options Registers (PSORA-POSRD)
      • Table 40-4. PSORx Field Descriptions
  • 40.3 Port Block Diagram
    • Figure 40-6. Port Functional Operation
  • 40.4 Port Pins Functions
    • 40.4.1 General Purpose I/O Pins
    • 40.4.2 Dedicated Pins
  • 40.5 Ports Tables
    • Figure 40-7. Primary and Secondary Option Programming
    • Table 40-5. Port A-Dedicated Pin Assignment (PPARA = 1) (continued)
    • Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued)
    • Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
    • Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)
  • 40.6 Interrupts from Port C
• Appendix A Register Quick Reference Guide
  • A.1 PowerPC Registers-User Registers
  • A.2 PowerPC Registers-Supervisor Registers
  • A.3 MPC8260-Specific SPRs
• Appendix B Reference Manual (Rev 1) Errata
  • B.1 Document Errata
• Glossary
• Index