Renesas SH7781 - Manual (Page 1000)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 970 of 1658
REJ09B0261-0100
Figure 20.1 shows the GDTA block diagram.
SuperHyway bus
External memory
Target interface Initiator interface
(external) (external)
Control
register
Buffer RAM
interface
RAM 0 interface
arbiter
CL/MC
interface
Buffer
RAM 0
(8 Kbytes)
Buffer
RAM 1
(8 Kbytes)
CL
function block
MC
function block
RAM 1 interface
arbiter
Request
queue
(4 planes)
Response
queue
(4 planes)
Color conversion
table control
IDCT control
Arbiter
CPU LBSC DDR2-SDRAM DDR2IF
CLW-
GADMAC
CLR-
GADMAC
MCW-
GADMAC
MCR-
GADMAC
GDTA
Figure 20.1 GDTA Block Diagram