Renesas SH7781 - Manual (Page 15)

Rev.1.00 Jan. 10, 2008 Page xv of xxx
REJ09B0261-0100
11.5.9 Bus Arbitration ................................................................................................... 448
11.5.10 Master Mode....................................................................................................... 450
11.5.11 Slave Mode ......................................................................................................... 451
11.5.12 Cooperation between Master and Slave.............................................................. 451
11.5.13 Power-Down Mode and Bus Arbitration ............................................................ 451
11.5.14 Mode Pin Settings and General Input Output Port Settings about
Data Bus Width................................................................................................... 452
11.5.15 Pins Multiplexed with Other Modules Functions ............................................... 452
11.5.16 Register Settings for Divided-Up
DACKn Output ............................................. 452
Section 12 DDR2-SDRAM Interface (DBSC2) .......................................................... 457
12.1 Features.............................................................................................................................. 457
12.2 Input/Output Pins ............................................................................................................... 460
12.3 Data Alignment.................................................................................................................. 465
12.4 Register Descriptions ......................................................................................................... 479
12.4.1 DBSC2 Status Register (DBSTATE) ................................................................. 482
12.4.2 SDRAM Operation Enable Register (DBEN)..................................................... 483
12.4.3 SDRAM Command Control Register (DBCMDCNT) ....................................... 484
12.4.4 SDRAM Configuration Setting Register (DBCONF)......................................... 486
12.4.5 SDRAM Timing Register 0 (DBTR0) ................................................................ 488
12.4.6 SDRAM Timing Register 1 (DBTR1) ................................................................ 492
12.4.7 SDRAM Timing Register 2 (DBTR2) ................................................................ 495
12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) .......................................... 499
12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1) .......................................... 500
12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) .......................................... 502
12.4.11 SDRAM Refresh Status Register (DBRFSTS) ................................................... 504
12.4.12 DDRPAD Frequency Setting Register (DBFREQ) ............................................ 505
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)..................... 507
12.4.14 SDRAM Mode Setting Register (DBMRCNT) .................................................. 510
12.5 DBSC2 Operation .............................................................................................................. 512
12.5.1 Supported SDRAM Commands.......................................................................... 512
12.5.2 SDRAM Command Issue ................................................................................... 513
12.5.3 Initialization Sequence........................................................................................ 516
12.5.4 Self-Refresh Operation ....................................................................................... 517
12.5.5 Auto-Refresh Operation...................................................................................... 520
12.5.6 Regarding Address Multiplexing........................................................................ 521
12.5.7 Regarding SDRAM Access and Timing Constraints.......................................... 530
12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products ..... 544
12.5.9 Important Information Regarding ODT Control Signal Output to SDRAM ...... 544
12.5.10 DDR2-SDRAM Power Supply Backup Function............................................... 546