Renesas SH7781 - Manual (Page 791)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 761 of 1658
REJ09B0261-0100
16.2 Input/Output Pins
Table 16.1 shows the pin configuration of the WDT module.
Table 16.1 Pin Configuration
Pin name Function I/O Description
PRESET
Power-on reset input Input A low level input to this pin places the LSI in
the power-on reset state.
MRESETOUT
Manual reset output Output Low level is output during manual reset
execution.
This pin is multiplexed with the
IRQOUT
(INTC) pin.
Indicate the LSI's operating status
STATUS1
High
High
Low
STATUS0
High
Low
Low
Operating Status
Reset
Sleep mode
Normal operation
STATUS[1:0] Status output Output
The STATUS1 pin is multiplexed with the
DRAK1 (DMAC) and PK6 (GPIO) pins.
The STATUS0 pin is multiplexed with the
DRAK0 (DMAC) and PK7 (GPIO) pins.