Renesas SH7781 - Manual (Page 405)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 375 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value
R/W Description
9, 8 SZ 11 R/W* Bus Width
In CS0BCR, the external pins (MODE5 and MODE6) to
specify the bus size are sampled at a power-on reset.
When using the MPX interface, set these bits to 00 or
11. When using the byte control SRAM interface, set
these bits to 00, 10 or 11.
00: 64 bits (can be specified when the MODE 12 and
MODE 11 pins are set to 1 and 0 respectively.)
01: 8 bits
10: 16 bits
11: 32 bits
Note: * The SZ bits in CS0BCR are read-only. When
area 0 is set to the MPX interface by the
MODE7 pin, the SZ bits in CS0BCR should be
set to 00 or 11.
7 RDSPL 1 R/W
RD Hold Cycle
Specifies the number of cycles to be inserted in the
hold time for the read data sample timing of
RD. When
setting this bit to 1, specify the number of
RD negation-
CSn negation delay cycles set by the RDH bit in
CSnWCR as 1 or more. Also the
RD negation-CSn
negation delay cycle is reduced 1 cycle when this bit is
set to 1 (valid only when the SRAM interface, burst
ROM interface, or byte control SRAM interface is
selected).
0: No hold cycle inserted
1: 1 hold cycle inserted