Renesas SH7781 - Manual (Page 520)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 490 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
14 to 8 TRFC6 to
TRFC0 000 0101 R/W tRFC (REF-ACT/REF period) Setting Bits
These bits set the REF-ACT/REF minimum period
constraint These bits should be set according to the
DDR2-SDRAM specifications. The number of cycles is
the number of DDR clock cycles.
000 0000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
000 0100: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
000 0101: 6 cycles
000 0110: 7 cycles
:
100 0001: 66 cycles
100 0010: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111 1111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
7 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.