Renesas SH7781 - Manual (Page 42)

1. Overview
Rev.1.00 Jan. 10, 2008 Page 12 of 1658
REJ09B0261-0100
Item Features
Serial sound
interface (SSI)
• Number of channels: Two (max.)
• Supports transfer of compressed and non-compressed data
• Selectable frame size
NAND flash
memory
controller (FLCTL) • Number of channels: One (max.)
• Exclusively for NAND-type flash memory
• Operating modes: Command-access mode, sector-access mode
• Data transfer FIFOs
⎯ On-chip 224-byte FIFO for transfer of data to and from flash memory
⎯ On-chip 32-byte FIFO for transfer of control codes
⎯ Flag bit to indicate overruns and underruns during access from the
CPU or DMA
General purpose
I/O (GPIO) • General purpose I/O port pins: 111
• Some GPIO pins are configurable as interrupts
User break
controller (UBC) • Supports user-break interrupts as a facility for debugging
• Two break channels
• Addresses, data values, types of access, and widths of data are all
specifiable as break conditions
• Supports a sequential break function
User debug
interface (H-UDI) • JTAG interface (TCK, TMS, TRST, TDI, TDO)
• Supports the E10A emulator
• Realtime branch tracing
Package • 436-pin flip-chip BGA (body: 19 x 19 mm, ball pitch: 0.8-mm)
Power supply
voltage • Internal (VDD), PLL1 (VDD-PLL1, VDDA-PLL1), PLL2 (VDD-PLL2):
1.1 V
• DDR2 I/O (VDD-DDR): 1.8 V
• I/O (VDDQ), PLL1 (VDDQ-PLL1), PLL2 (VDDQ-PLL2): 3.3 V