Renesas SH7781 - Manual (Page 1587)

31. Register List
Rev.1.00 Jan. 10, 2008 Page 1557 of 1658
REJ09B0261-0100
Module
Name Name Abbrev.
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Manual Reset
by
WDT/Multiple
Exception
Sleep/
Deep Sleep by
SLEEP
Instruction
Module
Standby
HAC Command/status data register 1 HACCSDR1 H'0000 0000 H'0000 0000 Retained Retained
PCM left channel register 1 HACPCML1 H'0000 0000 H'0000 0000 Retained Retained
PCM right channel register 1 HACPCMR1 H'0000 0000 H'0000 0000 Retained Retained
TX interrupt enable register 1 HACTIER1 H'0000 0000 H'0000 0000 Retained Retained
TX status register 1 HACTSR1 H'F000 0000 H'F000 0000 Retained Retained
RX interrupt enable register 1 HACRIER1 H'0000 0000 H'0000 0000 Retained Retained
RX status register 1 HACRSR1 H'0000 0000 H'0000 0000 Retained Retained
HAC control register 1 HACACR1 H'8400 0000 H'8400 0000 Retained Retained
SSI Control register 0 SSICR0 H'0000 0000 H'0000 0000 Retained Retained
Status register 0 SSISR0 H'0200 0003 H'0200 0003 Retained Retained
Transmit data register 0 SSITDR0 H'0000 0000 H'0000 0000 Retained Retained
Receive data register 0 SSIRDR0 H'0000 0000 H'0000 0000 Retained Retained
Control register 1 SSICR1 H'0000 0000 H'0000 0000 Retained Retained
Status register 1 SSISR1 H'0200 0003 H'0200 0003 Retained Retained
Transmit data register 1 SSITDR1 H'0000 0000 H'0000 0000 Retained Retained
Receive data register 1 SSIRDR1 H'0000 0000 H'0000 0000 Retained Retained
FLCTL Common control register FLCMNCR H'0000 0000 H'0000 0000 Retained Retained
Command control register FLCMDCR H'0000 0000 H'0000 0000 Retained Retained
Command code register FLCMCDR H'0000 0000 H'0000 0000 Retained Retained
Address register FLADR H'0000 0000 H'0000 0000 Retained Retained
Data register FLDATAR H'0000 0000 H'0000 0000 Retained Retained
Data counter register FLDTCNTR H'0000 0000 H'0000 0000 Retained Retained
Interrupt DMA control register FLINTDMACR H'0000 0000 H'0000 0000 Retained Retained
Ready busy timeout setting register FLBSYTMR H'0000 0000 H'0000 0000 Retained Retained
Ready busy timeout counter FLBSYCNT H'0000 0000 H'0000 0000 Retained Retained
Data FIFO register FLDTFIFO Undefined Undefined Retained Retained
Control code FIFO register FLECFIFO Undefined Undefined Retained Retained
Transfer control register FLTRCR H'00 H'00 Retained Retained
Address register 2 FLADR2 H'0000 0000 H'0000 0000 Retained Retained