Renesas SH7781 - Manual (Page 738)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 708 of 1658
REJ09B0261-0100
Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. As channel 0 has a higher priority, the channel 0 transfer starts (channel 3 is waiting for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are waiting
for transfer).
4. When the channel 0 transfer ends, channel 0 has the lowest priority.
5. As channel 1 has a higher priority than channel 3 at this point, the channel 1 transfer starts
(channel 3 is waiting for transfer).
6. When the channel 1 transfer ends, channel 1 has the lowest priority.
7. The channel 3 transfer starts.
8. When the channel 3 transfer ends, channels 3 and 2 have lower priority so that channel 3 has
the lowest priority.
Transfer request Waiting channel(s) DMAC operation Channel priority
(1) Channels 0 and 3
(3) Channel 1
0 > 1 > 2 > 3 > 4 > 5 (2) Channel 0 transfer
start
(4) Channel 0 transfer
ends
(5) Channel 1 transfer
starts
(6) Channel 1 transfer
ends
(7) Channel 3 transfer
starts
(8) Channel 3 transfer
ends
1 > 2 > 3 > 4 > 5 > 0
2 > 3 > 4 > 5 > 0 > 1
4 > 5 > 0 > 1 > 2 > 3
Priority order
changes
Priority order
changes
Priority order
changes None
3
3
1,3
Figure 14.3 Changes in Channel Priority in Round-Robin Mode
(Example of Channels 0 to 5)