Renesas SH7781 - Manual (Page 320)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 290 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W Description
2 IM102 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HHLH
(H'D).
1 IM101 0 R/W Masks the interrupt source
of
IRL7 to IRL4 = HHHL
(H'E).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
0 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.