Renesas SH7781 - Manual (Page 1388)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1358 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
3 BTOINTE 0 RW Interrupt Enable at Timeout Error
Enables or disables an interrupt request to the CPU
when a timeout error has occurred.
0: Disables the interrupt request to the CPU by a
timeout error
1: Enables the interrupt request to the CPU by a
timeout error
2 TEINTE 0 R/W Transfer End Interrupt Enable
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables an interrupt to the CPU at the end of a
transfer
1: Enables an interrupt to the CPU at the end of a
transfer
1 TRINTE1 0 R/W FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request from FLECFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLECFIFO.
1: Enables an interrupt request to the CPU by a transfer
request from FLECFIFO.
When the DMA transfer is enabled, this bit should be
cleared to 0.
0 TRINTE0 0 R/W FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLDTFIFO
1: Enables an interrupt request to the CPU by a transfer
request from FLDTFIFO
When the DMA transfer is enabled, this bit should be
cleared to 0.