Renesas SH7781 User Manual
Page 928
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 898 of 1658
REJ09B0261-0100
19.3.32
Plane n Memory Width Register (PnMWR) (n
= 1 to 6)
The plane n memory width registers (PnMWR, n = 1 to 6) set the memory width for plane n.
The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
O
O
O
O
O
O
O
O
O
0
0
0
0
—
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
PnMWX
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Internal
Update Description
31 to 13
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
12 to 4
PnMWX
Undefined R/W
Yes
Plane n Memory Width X
The plane n memory width should be set in the
range 16 pixels to 4096 pixels, in 16-pixel units.
3 to 0
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.