Renesas SH7781 - Manual (Page 621)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 591 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
10 FTO 0 SH: R/W
PCI: R
PCI
TRDY/Control Enable
Specifies the function that negates
TRDY within 5
cycles before disconnection in a target access.
0: Disabled
1: Enabled
9 PFE 0 SH: R/W
PCI: R
PCI Pre-Fetch Enable
Specifies whether pre-fetch is performed when a
target memory access is performed by an external
PCI device.
0: Disabled
1: Enabled
8 TBS 0 SH: R/W
PCI: R
Byte Swap
Specifies whether byte data is swapped when the PCI
bus is accessed.
0: No swap
1: Byte data is swapped
For details, see section 13.4.3 (5), Endian or
section 13.4.4 (6), Endian.
7
⎯ 0 SH:
R
PCI: R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 BMAM 0 SH: R/W
PCI: R
Bus Master Arbitration
Controls the PCI bus arbitration mode of the PCIC
when the PCIC is in host mode. This bit is ignored
when the PCIC is in normal mode.
Note: For details, see section 13.4.5 (3), Arbitration.
0: Priority fixed mode (PCIC > device0 > device1 >
device2 > device3)
1: Pseudo-round-robin (the priority of the device that
has bus mastership is set to the lowest.)
5 to 3
⎯ xxx
SH: R
PCI: R
Reserved
These bits are always read as an undefined value.
The write value should always be 0.