Renesas SH7781 - Manual (Page 1186)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1156 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
5 IDIV 0 R/W Initial Clock Division Ratio
0: The peripheral clock (Pck) is divided by a factor of 4
initially to create an intermediate frequency, which is
further divided to create the serial clock for master
mode.
1: The peripheral clock (Pck) is divided by a factor of 32
initially to create an intermediate frequency, which is
further divided to create the serial clock for master
mode.
4 to 0 CLKC4 to
CLKC0 All 0 R/W Clock Division Count
These bits determine the frequency dividing ratio that is
used to obtain the serial clock from the intermediate
clock.
00000: 1 intermediate frequency cycle.
Serial clock frequency = Intermediate
frequency / 2.
00001: 2 Intermediate frequency cycles.
Serial clock frequency = Intermediate
frequency / 4.
00010: 3 intermediate frequency cycles.
Serial clock frequency = Intermediate
frequency / 6.
: :
11111: 32 intermediate frequency cycles.
Serial clock frequency = Intermediate
frequency / 64.