Renesas SH7781 - Manual (Page 1189)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1159 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
8 TXEM 1 R Transmit FIFO Empty Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the transmit FIFO is empty of data to
transmit. It is cleared to 0 when data is written to the
transmit FIFO.
If TXEM = 1 and TEIE = 1, an interrupt is generated.
7 RXFU 0 R Receive FIFO Full Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO is full of received
bytes and cannot accept any more. It is cleared to 0
when data is read out of the receive FIFO.
If RXFU = 1 and RFIE = 1, an interrupt is generated.
6 RXHA 0 R Receive FIFO Halfway Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO reaches the halfway
point, that is, it has four bytes of data and free space for
four bytes of data. This flag is cleared to 0 when the
receive data is read from receive FIFO and the data
stored in the FIFO becomes less than four bytes
(halfway point).
If RXHA = 1 and RHIE = 1, an interrupt is generated.
5 RXEM 1 R Receive FIFO Empty Flag
This status flag is enabled only in FIFO mode. The flag
is set to 1 when the receive FIFO is empty of received
data. It is cleared to 0 when data is written to the
receive FIFO.
If RXEM = 0 and RNIE = 1, an interrupt is generated.
4 RXOO 0 R/W* Receive Buffer Overrun Occurred Flag
This status flag is set to 1 when new data has been
received but the previous received data has not been
read from SPRBR. The previously received data will not
be overwritten by the newly received data. The RXOO
flag remains set to 1 until writing 0 to this bit position.
If RXOO = 1 and ROIE = 1, an interrupt is generated.