Renesas SH7781 User Manual
Page 360
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 330 of 1658
REJ09B0261-0100
Table 10.13 Interrupt Exception Handling and Priority
Interrupt Source
INTEVT
Code
Interrupt
Priority
Mask/Clear
Register & Bit
Interrupt
Source
Register
Detail
Source
Register
Priority
within
Sets of
Sources
Default
Priority
NMI
⎯ H'1C0
16
⎯
⎯
⎯ High
IRL[3:0] = LLLL (H'0)
H'200
15
INTMSK2[31]
INTMSKCLR2[31]
⎯
⎯ High
IRL[7:4] = LLLL (H'0)
H'B00
INTMSK2[15]
INTMSKCLR2[15]
⎯
⎯ Low
IRL[3:0] = LLLH (H'1) H'220
14
INTMSK2[14]
INTMSKCLR2[14]
⎯
⎯ High
IRL[7:4] = LLLH (H'1) H'B20
INTMSK2[30]
INTMSKCLR2[30]
⎯
⎯ Low
IRL[3:0] = LLHL (H'2) H'240
13
INTMSK2[13]
INTMSKCLR2[13]
⎯
⎯ High
IRL[7:4] = LLHL (H'2) H'B40
INTMSK2[29]
INTMSKCLR2[29]
⎯
⎯ Low
IRL
L: Low
level
input
H: High
level
input
(See
table
10.11)
IRL[3:0] = LLHH (H'3) H'260
12
INTMSK2[12]
INTMSKCLR2[12]
⎯
⎯ High
IRL[7:4] = LLHH (H'3) H'B60
INTMSK2[28]
INTMSKCLR2[28]
⎯
⎯ Low
IRL[3:0] = LHLL (H'4) H'280
11
INTMSK2[11]
INTMSKCLR2[11]
⎯
⎯ High
IRL[7:4] = LHLL (H'4) H'B80
INTMSK2[27]
INTMSKCLR2[27]
⎯
⎯ Low
IRL[3:0] = LHLH (H'5) H'2A0
10
INTMSK2[10]
INTMSKCLR2[10]
⎯
⎯ High
IRL[7:4] = LHLH (H'5) H'BA0
INTMSK2[26]
INTMSKCLR2[26]
⎯
⎯ Low
IRL[3:0] = LHHL (H'6) H'2C0
9
INTMSK2[9]
INTMSKCLR2[9]
⎯
⎯ High
IRL[7:4] = LHHL (H'6) H'BC0
INTMSK2[25]
INTMSKCLR2[25]
⎯
⎯ Low
IRL[3:0] = LHHH (H'7) H'2E0
8
INTMSK2[8]
INTMSKCLR2[8]
⎯
⎯ High
IRL[7:4] = LHHH (H'7) H'BE0
INTMSK2[24]
INTMSKCLR2[24]
⎯
⎯ Low
Low