Renesas SH7781 - Manual (Page 1364)

26. Serial Sound Interface (SSI) Module
Rev.1.00 Jan. 10, 2008 Page 1334 of 1658
REJ09B0261-0100
When an underflow or overflow error condition is met (UIRQ = 1 or OIRQ = 1), the CHNO[1:0]
and SWNO bits can be used to recover the SSI module to a known status. When an underflow or
overflow occurs, the CPU can read the number of channels and the number of system words to
determine what point the serial audio stream has currently reached. In the transmitter case, the
CPU can skip forward through the data it wants to transmit until the transmit of the data for which
the SSI module is expecting to transmit next is enabled, and so resynchronize with the audio data
stream. In the receiver case, the CPU can skip forward storing null sample data until it is ready to
store the sample data that the SSI module will receive next to ensure consistency of the number of
received data, and so resynchronize with the audio data stream.
26.4.7 Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode, then
the bit clock that is used in the shift register is derived from the SSI_SCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI module is in clock master mode,
and the shift register uses the bit clock derived from the SSI_CLK input pin or its clock divided.
This input clock is then divided by the ratio in the serial oversampling clock division ratio
(CKDV) bits in SSICR and used as the bit clock in the shift register.
In either case, the SSI_SCK pin output is the same as the bit clock.