Renesas SH7781 - Manual (Page 888)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 858 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
18 CP3CE 0 R/W Yes Color Palette 3 Change Enable
0: Switching of color palette 3 is not performed.
1: Switching of color palette 3 is performed.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 3,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
17 CP2CE 0 R/W Yes Color Palette 2 Change Enable
0: Switching of color palette 2 is not performed.
1: Switching of color palette 2 is performed.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 2,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
16 CP1CE 0 R/W Yes Color Palette 1 Change Enable
0: Switching of color palette 1 is not performed.
1: Switching of color palette 1 is performed.
Switching is performed when the DRES bit in
DSYSR is changed from 1 to 0, or with the
timing of an internal update. This bit can only
be set to 1; an operation to set the bit to 0 is
invalid. After switching of the color palette 1,
the bit is cleared to 0.
When setting to 1 and clearing occur
simultaneously, clearing to 0 takes priority.
15 to 0
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.