Renesas SH7781 - Manual (Page 1380)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1350 of 1658
REJ09B0261-0100
• Sector access mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
ADR[25:16]
ADR[15:0]
Bit Bit Name
Initial
Value R/W
Description
31 to 26 — All 0 R Reserved
These bits are undefined depending on the operation
mode of the FLCTL.
25 to 0 ADR[25:0] All 0 R/W Physical Sector Address
Specify a physical sector number to be accessed in
sector access mode. The physical sector number is
converted into an address and is output to flash
memory. When the ADRCNT2 bit in FLCMDCR is 1,
ADR25 to ADR0 are valid. When the ADRCNT2 bit in
FLCMDCR is 0, ADR17 to ADR0 are valid.