Renesas SH7781 - Manual (Page 1539)

31. Register List
Rev.1.00 Jan. 10, 2008 Page 1509 of 1658
REJ09B0261-0100
Section 31 Register List
This section is a summary of the contents of the descriptions of on-chip I/O registers in the
individual sections.
31.1 Register Address List
The addresses of the I/O registers incorporated in the SH7785 are listed in table 31.1. The registers
are grouped by functional module, and these appear in the same order as the sections of the
manual. Since this is a summary, parts of the descriptions, along with the notes, have been
omitted. For details on the registers, refer to the descriptions in the corresponding sections.
Notes: 1. Access to undefined and reserved addresses is prohibited.
2. Access in an access unit other than that specified in this list is prohibited.
3. The register addresses are given as the P4-area address (the P4 area of the virtual
address space) and the area-7 address (accessed in area 7 of the physical address space
by using the TLB).
4. In the case of the PCIC module, entries under "R/W" indicate the state of the
SuperHyway bus in which the given register is accessed.