Renesas SH7781 - Manual (Page 362)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 332 of 1658
REJ09B0261-0100
Interrupt Source
INTEVT
Code
Interrupt
Priority
Mask/Clear
Register & Bit
Interrupt
Source
Register
Detail
Source
Register
Priority
within
Sets of
Sources
Default
Priority
IRQ IRQ[0] H'240 INTPRI
[31:28]
INTMSK0[31]
INTMSKCLR0
[31]
INTREQ
[31]
⎯ High
IRQ[1] H'280 INTPRI
[27:24]
INTMSK0[30]
INTMSKCLR0
[30]
INTREQ
[30]
⎯
IRQ[2] H'2C0 INTPRI
[23:20]
INTMSK0[29]
INTMSKCLR0
[29]
INTREQ
[29]
⎯
IRQ[3] H'300 INTPRI
[19:16]
INTMSK0[28]
INTMSKCLR0
[28]
INTREQ
[28]
⎯
IRQ[4] H'340 INTPRI
[15:12]
INTMSK0[27]
INTMSKCLR0
[27]
INTREQ
[27]
⎯
IRQ[5] H'380 INTPRI
[11:8]
INTMSK0[26]
INTMSKCLR0
[26]
INTREQ
[26]
⎯
IRQ[6] H'3C0 INTPRI
[7:4]
INTMSK0[25]
INTMSKCLR0
[25]
INTREQ
[25]
⎯
IRQ[7] H'200 INTPRI
[3:0]
INTMSK0[24]
INTMSKCLR0
[24]
INTREQ
[24]
⎯
WDT ITI* H'560 INT2PRI3
[12:8]
INT2MSKR[8]
INT2MSKCR[8]
INT2A0[8]
INT2A1[8]
⎯
TMU-ch0 TUNI0* H'580 INT2PRI0
[28:24]
INT2B0[0]
TMU-ch1 TUNI1* H'5A0 INT2PRI0
[20:16]
INT2B0[1]
TMU-ch2 TUNI2* H'5C0 INT2PRI0
[12:8]
INT2B0[2]
TICPI2* H'5E0 INT2PRI0
[4:0]
INT2MSKR[0]
INT2MSKCLR
[0]
INT2A0[0]
INT2A1[0]
INT2B0[3]
H-UDI H-UDII H'600 INT2PRI4
[28:24]
INT2MSKR[9]
INT2MSKCLR
[9]
INT2A0[9]
INT2A1[9]
⎯
Low