Renesas SH7781 - Manual (Page 583)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 553 of 1658
REJ09B0261-0100
Figure 13.1 shows a block diagram of the PCIC.
PCI b
us
PCIC module
Inter
nal b
us (SHwyb
us)
SHwy bus
interface
Data FIFO
read
32 bytes x 2
PCIECR
Data FIFO
write
32 bytes x 2
SHwy clock input
Interrupt control
Interrupt
Target control
Register control
Configuration
registers
/local registers
Master control PCI b
us interf
ace
(PCI b
us access control)
AD[31:0]
CBE[3:0]
PAR
INTA
INT[B:D]
REQ0/REQOUT
GNT0/GNTIN
REQ[3:1]
GNT[3:1]
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
LOCK
IDSEL
PCIRESET
PCICLK input
Figure 13.1 Block Diagram of PCIC
The PCIC comprises two blocks, the PCI bus interface block and SuperHyway bus interface
block.
The PCI bus interface block comprises the PCI configuration register, local register, PCI master
controller, and PCI target controller.
The SuperHyway bus interface converts the access from the PCI bus interface into the access to
the SuperHyway bus, and converts the access from the SuperHyway bus (the CPU or DMAC) into
access to the PCI bus interface block. The SuperHyway bus interface block comprises PCIECR,
the access control block from the SuperHyway bus to the PCI bus, and the access control block
from the PCI bus to the SuperHyway bus.
The interrupt controller controls the issue of interrupts to INTC of this LSI.