7 execution count break register 1 (cetr1) – Renesas SH7781 User Manual
Page 1500
29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1470 of 1658
REJ09B0261-0100
29.2.7
Execution Count Break Register 1 (CETR1)
CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before
a break occurs. A maximum value of 2
12
–
1 can be specified. When the execution count value is
included in the match conditions by using the match condition setting register, the value of this
register is decremented by one every time the channel is hit. When the channel is hit after the
register value reaches H'001, a break occurs.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CET
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit :
Initial value :
R/W:
Bit :
Initial value :
R/W:
Bit Bit
Name
Initial
Value
R/W
Description
31 to 12 —
All 0
R
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
11 to 0 CET
Undefined R/W
Execution Count
Specifies the execution count to be included in the break
conditions.