Renesas SH7781 - Manual (Page 1113)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1083 of 1658
REJ09B0261-0100
In serial reception, the SCIF operates as follows.
1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
(a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
(b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
(c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
error has occurred.*
(d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
set.*
If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.
Note: * Reception continues even when a parity error or framing error occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Figure 21.13 shows an example of the operation for reception in asynchronous mode.
1
0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/1 0
RDF
FER
Framing error
detected
Serial
data
SCIF_RXD
Start
bit Data Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler ERI interrupt request
generated by receive
error
Figure 21.13 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)