Renesas SH7781 - Manual (Page 515)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 485 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
2 to 0 CMD2 to
CMD0 000 R/W SDRAM Command Issue Bit
These bits are used to issue commands necessary to
execute the DDR2-SDRAM initialization sequence and
self-refresh transition/cancellation. When these bits are
written, the command corresponding to the written value
is issued once. For example, in order to issue the auto-
refresh command twice, it would be necessary to write
100 to these bits twice. The precharge interval,
minimum interval between auto-refresh and the next
command, and other intervals are values set in the
SDRAM timing register, described below. When read,
these bits are always read as 000.
Once writing is performed to enable the MCKE signal, it
remains enabled. During self-refresh control, the MCKE
goes to low level, but on cancellation MCKE
automatically returns to high level.
For details on the MCKE signal operation, refer to
section 12.5.13, Regarding MCKE Signal Operation.
000: Normal operation (power-on reset)
001: Setting prohibited (Correct operation cannot be
guaranteed.)
010: Precharge (PALL) command issued
011: The MCKE signal is enabled (high level).
100: Auto-refresh (REF) command issued
101 to 111: Setting prohibited (Correct operation cannot
be guaranteed.)
Note: This register can be written only when automatic issue of auto-refresh is disabled (the
ARFEN bit in the DBRFCNT0 register is cleared to 0).