Renesas SH7781 - Manual (Page 632)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 602 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
0 MRDPEI 0 SH: R/WC
PCI: R
Master Read Data Parity Error Interrupt
Indicates that the PCIC detected a parity error during
data read from the target when the PCIC is a master.
Note: A master read data parity error is detected only
when bit 6 (PER) in PCICMD is set to 1.
0: A master read data parity error interrupt was not
generated
1: A master read data parity error interrupt was
generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.