Renesas SH7781 - Manual (Page 472)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 442 of 1658
REJ09B0261-0100
A18 to A3
CSn
RD
R/ W
SH7785
64K × 16 bits
SRAM
D47 to D32
WE5
WE4
D31 to D16
WE3
WE2
D15 to D0
WE1
WE0
A15 to A0
CS
OE
WE
I/O15 to I/O0
UB
LB
A15 to A0
CS
OE
WE
I/O15 to I/O0
UB
LB
A15 to A0
CS
OE
WE
I/O15 to /O0
UB
LB
A15 to A0
CS
OE
WE
I/O15 to I/O0
UB
LB
D63 to D48
WE7
WE6
Figure 11.37 Example of Byte Control SRAM with 64-Bit Data Width