Renesas SH7781 - Manual (Page 439)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 409 of 1658
REJ09B0261-0100
When software wait insertion is specified by CSnWCR, the external wait input signal,
RDY, is
also sampled. The
RDY signal sampling timing is shown in figure 11.10, where a single wait cycle
is specified as a software wait. The
RDY signal is sampled at the transition from the Tw state to
the T2 state. Therefore, the assertion of the
RDY signal has no effect in the T1 cycle or in the first
Tw cycle. The
RDY signal is sampled on the rising edge of the clock.
T1
CLKOUT
A25 to A0
CSn
R/ W
RD
(In reading)
D31 to D0
(In reading)
WEn
(In writing)
D31 to D0
(In writing)
BS
Tw Twe T2
RDY
DACKn
In this example, DACKn is active-high. (The circles indicate the sampling timing.)
: Sampling Timing
Figure 11.10 SRAM Interface Wait Timing
(Wait Cycle Insertion by
RDY Signal, RDY Signal Is Synchronous Input)