Renesas SH7781 - Manual (Page 759)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 729 of 1658
REJ09B0261-0100
14.5 DMAC Interrupt Sources
In the DMAC, each channel has 14 interrupt sources: a DMA transfer end/half-end interrupts
request (DMINT0 to DMINT11), a DMA address error interrupt request (DMAE0) common to
channels 0 to 5, and a DMA address error interrupt request (DMAE1) common to channels 6 to
11.
Table 14.11 shows each interrupt source. Each interrupt source is independently sent to the
interrupt controller.
Table 14.11 DMAC Interrupt Sources
Interrupt Factor Description
DMINT0 Channel 0 DMA transfer-end/half-end interrupt
DMINT1 Channel 1 DMA transfer-end/half-end interrupt
DMINT2 Channel 2 DMA transfer-end/half-end interrupt
DMINT3 Channel 3 DMA transfer-end/half-end interrupt
DMINT4 Channel 4 DMA transfer-end/half-end interrupt
DMINT5 Channel 5 DMA transfer-end/half-end interrupt
DMAE0 DMA address error interrupt common to channels 0 to 5
DMINT6 Channel 6 DMA transfer-end/half-end interrupt
DMINT7 Channel 7 DMA transfer-end/half-end interrupt
DMINT8 Channel 8 DMA transfer-end/half-end interrupt
DMINT9 Channel 9 DMA transfer-end/half-end interrupt
DMINT10 Channel 10 DMA transfer-end/half-end interrupt
DMINT11 Channel 11 DMA transfer-end/half-end interrupt
DMAE1 DMA address error interrupt common to channels 6 to 11