Renesas SH7781 - Manual (Page 902)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 872 of 1658
REJ09B0261-0100
19.3.17 Equal Pulse Width Register (EQWR)
The equal pulse width register (EQWR) sets the low-level pulse width of a pulse equivalent to the
CSYNC signal. The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R
O O O O O O O
— — — — — — — 0 0 0 0 0 0 0 0 0
EQW — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Internal
Update Description
31 to 7
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
6 to 0 EQW Undefined R/W Yes Equal Pulse Width
The low-level pulse width of a pulse equivalent
to the CSYNC signal should be set in dot clock
units.
To enable this setting, bit 1 of the CSY bits in
DSMR should be set to 1.