Renesas SH7781 - Manual (Page 1583)

31. Register List
Rev.1.00 Jan. 10, 2008 Page 1553 of 1658
REJ09B0261-0100
Module
Name Name Abbrev.
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Manual Reset
by
WDT/Multiple
Exception
Sleep/
Deep Sleep by
SLEEP
Instruction
Module
Standby
SCIF Serial port register 4 SCSPTR4 H'000x* 2 H'000x* 2 Retained Retained
Line status register 4 SCLSR4 H'0000 H'0000 Retained Retained
Serial error register 4 SCRER4 H'0000 H'0000 Retained Retained
Serial mode register 5 SCSMR5 H'0000 H'0000 Retained Retained
Bit rate register 5 SCBRR5 H'FF H'FF Retained Retained
Serial control register 5 SCSCR5 H'0000 H'0000 Retained Retained
Transmit FIFO data register 5 SCFTDR5 Undefined Undefined Retained Retained
Serial status register 5 SCFSR5 H'0060 H'0060 Retained Retained
Receive FIFO data register 5 SCFRDR5 Undefined Undefined Retained Retained
FIFO control register 5 SCFCR5 H'0000 H'0000 Retained Retained
Transmit FIFO data count register 5 SCTFDR5 H'0000 H'0000 Retained Retained
Receive FIFO data count register 5 SCRFDR5 H'0000 H'0000 Retained Retained
Serial port register 5 SCSPTR5 H'000x* 2 H'000x* 2 Retained Retained
Line status register 5 SCLSR5 H'0000 H'0000 Retained Retained
Serial error register 5 SCRER5 H'0000 H'0000 Retained Retained
SIOF Mode register SIMDR H'8000 H'8000 Retained Retained
Clock select register SISCR H'C000 H'C000 Retained Retained
Transmit data assign register SITDAR H'0000 H'0000 Retained Retained
Receive data assign register SIRDAR H'0000 H'0000 Retained Retained
Control data assign register SICDAR H'0000 H'0000 Retained Retained
Control register SICTR H'0000 H'0000 Retained Retained
FIFO control register SIFCTR H'1000 H'1000 Retained Retained
Status register SISTR H'0000 H'0000 Retained Retained
Interrupt enable register SIIER H'0000 H'0000 Retained Retained
Notes: 1. Bits 2 and 0 are undefined.
2. Bits 6, 4, 2 and 0 are undefined.