Renesas SH7781 - Manual (Page 429)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 399 of 1658
REJ09B0261-0100
For the number of bus cycles, 0 to 25 wait cycles to be inserted can be selected by CS1WCR.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS1BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (
RDY).
(when no cycles are inserted, the
RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for
CS1
assertion and the
CS1 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS1WCR. The
BS hold cycles can be set to 1 or 2 when the RDS
bits in CS1WCR are not 000 in reading and the WTS bits in CS1WCR are not 000 in writing.
(3)
Area 2
Area 2 is an area where bits 28 to 26 in the local bus address are 010.
The interface that can be set for this area is the SRAM, MPX, or burst ROM interface.
When the SRAM interface is used, a bus width of 8, 16, 32, 64 bits is selectable by bits SZ in
CS2BCR. When the MPX interface is used, a bus width of 32 or 64 bits should be selected by bits
SZ in CS2BCR.
When area 2 is accessed, the
CS2 signal is asserted.
In the case where the SRAM interface is set, the
RD signal, which can be used as OE, and write
control signals
WE0 to WE7 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted can be selected by CS2WCR.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS2WCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (
RDY).
(when no cycles are inserted, the
RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for
CS2
assertion and the
CS2 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS2WCR. The
BS hold cycles can be set to 1 or 2 when the RDS
bits in CS2WCR are not 000 in reading and the WTS bits in CS2WCR are not 000 in writing.