Renesas SH7781 - Manual (Page 720)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 690 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
11, 10
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
9, 8 PR[1:0] 00 R/W Priority Mode 1, 0
Determine the priority between channels when there
are transfer requests for multiple channels
simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 (DMAOR0)
CH6 > CH7 > CH8 > CH9 > CH10 > CH11
(DMAOR1)
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5 (DMAOR0)
CH6 > CH8 > CH9 > CH7 > CH10 > CH11
(DMAOR1)
10: Setting prohibited
11: Round-robin mode for CH0 to CH5 (DMAOR0)
Round-robin mode for CH6 to CH11 (DMAOR1)
When round-robin mode is specified, do not mix the
cycle steal mode and the burst mode in any channels
(channels 0 to 5) corresponding to DMAOR0. For any
channels corresponding to DMAOR1 (channels 6 to
11), only normal mode 2 in the cycle steal mode
(CHCR.LCKN
= 1, CHCR.TB = 0) can be specified.
7 to 3
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.