Renesas SH7781 - Manual (Page 432)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 402 of 1658
REJ09B0261-0100
CS5PCR. In addition, the number of wait cycles can be specified in the range from 0 to 50 cycles
by the PCWA/B bit. The number of wait cycles specified by CS5PCR is added to the value
specified by bits IW3 to IW0 in CS5WCR or bits PCIW3 to PCIW0 in CS5PCR.
(7) Area 6
Area 6 is an area where bits 28 to 26 in the local bus address are 110.
The interface is that can be set for this area is the SRAM, MPX, burst ROM, and PCMCIA
interface.
When the SRAM interface is used, a bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in
CS6BCR. When the MPX interface is used, a bus width of 32 bits should be selected by bits SZ in
CS6BCR. When the PCMCIA interface is used, select a bus width of 8 or 16 bits with SZ in
CS6BCR. For details, see section 11.3.2, Memory Bus Width.
When the SRAM interface is used, the
CS6 signal is asserted when area 6 is accessed. The RD
signal, which can be used as
OE, and write control signals WE0 to WE7 are also asserted. When
the PCMCIA interface is used, the
CE1B and CE2B signals, the RD signal (which can be used as
OE), and the WE0, WE1, WE2, and WE3 signals which can be used as REG, WE, IORD, and
IOWR, respectively are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS6WCR can be selected.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS6BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (
RDY).
(when no cycles are inserted, the
RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for
CS6
assertion and the
CS6 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS6WCR. The
BS hold cycles can be set to 1 or 2 when the RDS
bits in CS6WCR are not 000 in reading and the WTS bits in CS6WCR are not 000 in writing.
For the PCMCIA interface, the setup/hold time of the address,
CE1B and CE2B to the read/write
strobe signal can be specified within a range from 0 to 15 cycles by bits TEDA/B and TEHA/B in
CS6PCR. In addition, the number of wait cycles can be specified in the range from 0 to 50 cycles
by the PCWA/B bit. The number of wait cycles specified by CS6PCR is added to the value
specified by bits IW3 to IW0 in CS6WCR or bits PCIW3 to PCIW0 in CS6PCR.