Renesas SH7781 - Manual (Page 780)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 750 of 1658
REJ09B0261-0100
4. Set H'CF000001 in FRQCR0 to enable execution of the sequence that changes the frequency.
The sequence that changes the frequency starts.
5. The CLKOUTENB pin output changes to low level. After ten cycles of the peripheral clock
(Pck), an unstable clock is output to the CLKOUT pin.
6. When the oscillation of PLL circuit 2 is stable, wait for ten cycles of the peripheral clock
(Pck). Then output a high level signal to the CLKOUTENB pin.
7. When the WDT starts counting up and the value of WDTBCNT is equal to the value of
WDTBST, the LSI resumes operation.
8. When H'00000000 is read from FRQCR0, the sequence that changes the frequency has
finished. The internal clock has been changed to the clock with the specified division ratio.
Note: * When setting a value except H'0 in the MFC3 to MFC0 bits in FRQCR1 to change the
DDR clock frequency, switch SDRAM to the self-refreshing state before executing
step (2) above. For details on how to switch to or release the self-refreshing state, see
section 12, DDR2-SDRAM Interface (DBSC2).
CLKOUT
output
Ten peripheral clock cycles PLL circuit 2 oscillation starts
CLKOUTENB
output
Figure 15.2 Beginning of the Change of the Bus Clock Frequency
CLKOUT
output
Ten peripheral clock cycles Operation restarts
PLL circuit 2 stabilized oscillation Counting-up by the WDT
CLKOUTENB
output
Figure 15.3 End of the Change of the Bus Clock Frequency