Renesas SH7781 - Manual (Page 1523)

30. User Debugging Interface (H-UDI)
Rev.1.00 Jan. 10, 2008 Page 1493 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
15 to 1
⎯ All
0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 INTREQ 0 R/W Interrupt Request
Indicates whether or not an interrupt by an H-UDI
interrupt command has occurred. Clearing this bit to 0
by the CPU cancels an interrupt request. When writing
1 to this bit, the previous value is maintained.
30.3.3 Bypass Register (SDBPR)
SDBPR is a 1-bit register that supports the JTAG bypass mode. When the BYPASS command is
set to the boundary-scan TAP controller, SDBPR is connected between the TDI and TDO pins.
This register cannot be accessed through the CPU. This register is not initialized by a power-on
reset or assertion of
TRST, but it is initialized to 0 by the Capture-DR state.
30.3.4 Boundary Scan Register (SDBSR)
SDBSR is a register that supports the JTAG boundary scan mode. SDBSR is a shift register that is
located on the PAD, to control the input/output pins. By using the SAMPLE/PRELOAD and
EXTEST commands, this register can perform the boundary scan test that supports the JTAG
standard (IEEE 1149.1) with the subset. This register cannot be accessed through the CPU,
regardless of chip mode. This register is not initialized by a power-on reset or assertion of
TRST.