Renesas SH7781 - Manual (Page 139)

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 109 of 1658
REJ09B0261-0100
(5) Instruction TLB Protection Violation Exception
• Source: The access does not accord with the ITLB protection information (PR bits or EPR bits)
shown in table 5.6 and table5.7.
Table 5.6 ITLB Protection Information (TLB Compatible Mode)
PR Privileged Mode User Mode
0 Access possible Access not possible
1 Access possible Access possible
Table 5.7 ITLB Protection Information (TLB Extended Mode)
EPR [5], EPR [3] Execution Permission in Privileged Mode
11 Execution of instructions possible
10 Instruction fetch not possible
Execution of Rn access by ICBI possible
00 Execution of instructions not possible
EPR [2], EPR [0] Execution Permission in User Mode
11, 01 Execution of instructions possible
10 Instruction fetch not possible
Execution of Rn access by ICBI possible
00 Execution of instructions not possible
• Transition address: VBR + H'00000100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.