Renesas SH7781 - Manual (Page 1138)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1108 of 1658
REJ09B0261-0100
22.3.3 Transmit Data Register (SITDR)
SITDR is a 32-bit write-only register that specifies SIOF transmit data.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
— — — — — — — — — — — — — — — —
SITDL[15:0]
W W W W W W W W W W W W W W W W
W W W W W W W W W W W W W W W W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
— — — — — — — — — — — — — — — —
SITDR[15:0]
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 16 SITDL[15:0] Undefined W Left-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as left-channel data. The position of the
left-channel data in the transmit frame depends on the
value set in the TDLA bit in SITDAR.
• These bits are valid when the TDLE bit in SITDAR is
set to 1.
15 to 0 SITDR[15:0] Undefined W Right-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as right-channel data. The position of
the right-channel data in the transmit frame depends on
the value set in the TDRA bit in SITDAR.
• These bits are valid when the TDRE bit in SITDAR
is set to 1, and the TLREP bit in SITDAR is cleared
to 0.