Renesas SH7781 - Manual (Page 500)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 470 of 1658
REJ09B0261-0100
Table 12.5 Data Alignment for Access in Little Endian when External Data Bus Width Is
Set to 32 Bits
Access Size Address
MDQ31 to
MDQ24 MDQ23 to
MDQ16 MDQ15 to
MDQ8 MDQ7 to
MDQ0
Address 0 Data
7 to 0
Address 1 Data
7 to 0
Address 2 Data
7 to 0
Address 3 Data
7 to 0
Address 4 Data
7 to 0
Address 5 Data
7 to 0
Address 6 Data
7 to 0
Byte
Address 7 Data
7 to 0
Address 0 Data
15 to 8
Data
7 to 0
Address 2 Data
15 to 8
Data
7 to 0
Address 4 Data
15 to 8
Data
7 to 0
Word
Address 6 Data
15 to 8
Data
7 to 0
Longword Address 0 Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0
Address 4 Data
31 to 24
Data
23 to 16
Data
15 to 8
Data
7 to 0