4 address register (fladr) – Renesas SH7781 User Manual
Page 1379
27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1349 of 1658
REJ09B0261-0100
27.3.4
Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies an address to be output in command
access mode. In sector access mode, a physical sector number specified in the physical sector
address bits is converted into an address to be output.
• Command access mode
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
ADR[31:24]
ADR[23:16]
ADR[15:8]
ADR[7:0]
Bit Bit
Name
Initial
Value R/W Description
31 to 24 ADR[31:24] H'00
R/W
Fourth Address Data
Specify the fourth data to be output to flash memory as
an address in command access mode.
23 to 16 ADR[23:16] H'00
R/W
Third Address Data
Specify the third data to be output to flash memory as
an address in command access mode.
15 to 8
ADR[15:8]
H'00
R/W
Second Address Data
Specify the second data to be output to flash memory
as an address in command access mode.
7 to 0
ADR[7:0]
H'00
R/W
First Address Data
Specify the first data to be output to flash memory as an
address in command access mode.