1 external interrupt request registers – Renesas SH7781 User Manual
Page 307
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 277 of 1658
REJ09B0261-0100
10.3.1
External Interrupt Request Registers
(1)
Interrupt Control Register 0 (ICR0)
ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode
for the external interrupt input pins and NMI pin, and indicates the level being input on the NMI
pin.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
0
⎯
⎯
⎯
⎯
⎯
LVL
MODE
IRLM1
IRLM0
NMIE
NMIB
⎯
⎯
⎯
⎯
NMIL
MAI
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R/W
Bit:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W
Description
31
NMIL
Undefined R
NMI Input Level
Indicates the signal level being input on the NMI pin.
Reading this bit allows the user to know the NMI pin
level, and writing is invalid.
0: Low level is being input on the NMI pin
1: High level is being input on the NMI pin
30
MAI
0
R/W
MAI (mask all interrupts) Interrupt Mask
Specifies whether all interrupts are masked while the
NMI pin is at the low level regardless of the setting of
the BL bit in SR of the CPU.
0: Interrupts remain enabled even when the NMI pin
goes low
1: Interrupts are disabled when the NMI pin goes low
29 to 26
⎯ All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.