Renesas SH7781 - Manual (Page 528)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 498 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
3 to 0 WRRD3 to
WRRD0 0011 R/W WRITE-READ Command Minimum Interval Setting Bits
These bits set the WRITE-READ command minimum
interval constraint. These bits should be set according
to the SDRAM specifications. The number of cycles is
the number of DDR clock cycles.
0000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
0010: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
0011: 4 cycles
0100: 5 cycles
:
1010: 11 cycles
1011: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
1111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
Note: Writing to this register should be performed only when the following conditions are met.
• When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
• When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).