Renesas SH7781 - Manual (Page 959)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 929 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
2 to 0 SYNCA 0 R/W None SYNC* Output Timing Adjustment
000: Adjustment of output timing is not
performed.
The SYNC* signal is output at the rising
edge of the dot clock, with the reference
timing.
001: The SYNC* signal is output at the rising
edge, delayed one dot clock cycle relative
to the reference timing.
010: The SYNC* signal is output at the rising
edge, delayed two dot clock cycles relative
to the reference timing.
011: The SYNC* signal is output at the rising
edge, delayed three dot clock cycles
relative to the reference timing.
100: The SYNC* signal is output at the falling
edge, preceding the reference timing by 1/2
dot clock cycle.
101: The SYNC* signal is output at the falling
edge, delayed 1/2 dot clock cycle relative to
the reference timing.
110: The SYNC* signal is output at the falling
edge, delayed (1+1/2) dot clock cycles
relative to the reference timing.
111: The SYNC* signal is output at the falling
edge, delayed (2+1/2) dot clock cycles
relative to the reference timing.
Note: * HSYNC, VSYNC, CSYNC, ODDF
signals