Renesas SH7781 - Manual (Page 634)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 604 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
6 SDIM 0 SH: R/W
PCI: R
SERR Detection Interrupt Mask
0: SEDI disabled (masked)
1: SEDI enabled (not masked)
5 DPEITWM 0 SH: R/W
PCI: R
Data Parity Error Interrupt Mask for Target Write
0: DPEITW disabled (masked)
1: DPEITW enabled (not masked)
4 PEDITRM 0 SH: R/W
PCI: R
PERR Detection Interrupt Mask for Target Read
0: PEDITR disabled (masked)
1: PEDITR enabled (not masked)
3 TADIMM 0 SH: R/W
PCI: R
Target-Abort Interrupt Mask for Master
0: TADIM disabled (masked)
1: TADIM enabled (not masked)
2 MADIMM 0 SH: R/W
PCI: R
Master-Abort Interrupt Mask for Master
0: MADIM disabled (masked)
1: MADIM enabled (not masked)
1 MWPDIM 0 SH: R/W
PCI: R
Master Write Data Parity Error Interrupt Mask
0: MWPEDI disabled (masked)
1: MWPEDI enabled (not masked)
0 MRDPEIM 0 SH: R/W
PCI: R
Master Read Data Parity Error Interrupt Mask
0: MRDPEI disabled (masked)
1: MRDPEI enabled (not masked)