Renesas SH7781 - Manual (Page 67)

2. Programming Model
Rev.1.00 Jan. 10, 2008 Page 37 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
17 to 12 Cause 000000 R/W
11 to 7 Enable (EN) 00000 R/W
6 to 2 Flag 00000 R/W
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
Each time an FPU operation instruction is executed, the
FPU exception cause field is cleared to 0. When an
FPU exception occurs, the bits corresponding to FPU
exception cause field and flag field are set to 1. The
FPU exception flag field remains set to 1 until it is
cleared to 0 by software.
For bit allocations of each field, see table 2.2.
1, 0 RM 01 R/W Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved