9) pci cache line size register (pcicls) – Renesas SH7781 User Manual
Page 601
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 571 of 1658
REJ09B0261-0100
(8)
PCI Base Class Code Register (PCIBCC)
This field defines the base class code. For details of the class code, see appendix D in PCI Local
Bus Specification Revision 2.2.
0
1
2
3
4
5
6
7
x
x
x
x
x
x
x
x
BCC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
SH R/W:
R
R
R
R
R
R
R
R
PCI R/W:
Bit Bit
Name
Initial
Value R/W
Description
7 to 0
BCC
H'xx
SH: R/W
PCI: R
Base Class Code
These bits indicate the base class code. The initial
value is H'xx.
(9)
PCI Cache Line Size Register (PCICLS)
0
1
2
3
4
5
6
7
0
0
0
0
0
1
0
0
CLS
R
R
R
R
R
R
R
R
Bit:
Initial value:
SH R/W:
R
R
R
R
R
R
R
R
PCI R/W:
Bit Bit
Name
Initial
Value R/W
Description
7 to 0
CLS
H'20
SH: R
PCI: R
Cache Line Size
SBO and SDON are ignored because a memory
target does not support cache.