6 normal mode, 7 power management – Renesas SH7781 User Manual
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13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 651 of 1658
REJ09B0261-0100
The PCIC can retain error information on the PCI bus. When an error occurs, the error address is
stored in PCIAIR and the transfer type and command information are stored in PCICIR. When the
PCIC is in host mode, the bus master information at the error occurrence is stored in PCIBMIR.
The PCIC can retain only one error information. Therefore, when multiple errors occur, only the
first error information is retained and subsequent error information is not retained. The error
information is initialized by a power-on reset.
13.4.6
Normal Mode
In normal mode, the bus arbiter in the PCIC does not operate. The PCI bus arbitration is
performed by an external PCI bus arbiter.
The Bus master that performs bus parking is decided by the GNT signal output from the external
bus arbiter. If the master that performs bus parking and the master that starts the next transfer are
different, high-impedance state is generated for one clock cycle or more before the address phase.
The
GNT0/GNTIN pin is used for the GNT input to the PCIC, and the REQ0/REQOUT pin is
used for the REQ output from the PCIC.
13.4.7
Power Management
The PCIC has PCI power management configuration registers (supporting subsets in version 1.1).
The following shows the supported features:
• Supports the PCI power management control configuration registers
• Supports the power-down/restore request interrupts from a host device on the PCI bus
The PCIC supports seven configuration registers for PCI power management control. PCICP
indicates the address offset for the power management configuration registers. In the PCIC,
PCICP is fixed to H'40. PCICID, PCINIP, PCIPMC, PCIPMCSR, PCIPMCSRBSE and PCIPCDD
are power management registers. These registers support four states: power state D0 (normal state)
power state D1 (bus idle state) power state D2 (clock stopped state) and power state D3 (power
down mode).
Figure 13.18 shows power down state transitions on the PCI bus.